radeonsi: get the raster config from AMDGPU on SI

Not sure yet if we wanna do this on CIK and VI too.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index e55d864187d59b97cbfe06c2cbb97721f52603a2..84a54bb094f00c9141ce72adc55b0d4e8dc1b41b 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -301,6 +301,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
                sizeof(amdinfo->gb_tile_mode));
        info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
+       memcpy(info->pa_sc_raster_config, amdinfo->pa_sc_raster_cfg,
+              sizeof(info->pa_sc_raster_config));
+       info->pa_sc_raster_config_1 = amdinfo->pa_sc_raster_cfg1[0];
 
        memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
                sizeof(amdinfo->gb_macro_tile_mode));

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 06b0c77546653ae4301588e8fb7860ab4eb6ecc9..91d303aee40d40b7af28761e86fe7b6c8a52b3fa 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -96,6 +96,8 @@ struct radeon_info {
        uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
        uint32_t                    pipe_interleave_bytes;
        uint32_t                    enabled_rb_mask; /* GCN harvest config */
+       uint32_t                    pa_sc_raster_config[4]; /* per SE */
+       uint32_t                    pa_sc_raster_config_1;
 
        uint64_t                    max_alignment; /* from addrlib */
        /* Tile modes. */

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 4772df25d1f2dc4b96b79775b8a9008dc382a68a..24e509cda8b2b3cbb4578c55296312b93080d0ec 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4421,6 +4421,23 @@ si_write_harvested_raster_configs(struct si_context *sctx,
 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
 {
        struct si_screen *sscreen = sctx->screen;
+
+       /* On SI, set the raster config value from AMDGPU. */
+       if (sscreen->b.info.drm_major == 3 && sscreen->b.chip_class == SI) {
+               if (sscreen->b.info.max_se == 1) {
+                       si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
+                                      sscreen->b.info.pa_sc_raster_config[0]);
+               } else {
+                       for (unsigned se = 0; se < sscreen->b.info.max_se; se++) {
+                               si_set_grbm_gfx_index_se(sctx, pm4, se);
+                               si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
+                                              sscreen->b.info.pa_sc_raster_config[se]);
+                       }
+                       si_set_grbm_gfx_index_se(sctx, pm4, ~0);
+               }
+               return;
+       }
+
        unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
        unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
        unsigned raster_config, raster_config_1;