Add ConstEval defaultval feature

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 4d48b45eaee4566da7769fb4affd0fa2b0818f3c..0229f5045419abcbc42ae77bb22007605b17782a 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -36,8 +36,9 @@ struct ConstEval
        SigSet<RTLIL::Cell*> sig2driver;
        std::set<RTLIL::Cell*> busy;
        std::vector<SigMap> stack;
+       RTLIL::State defaultval;
 
-       ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
+       ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)
        {
                CellTypes ct;
                ct.setup_internals();
@@ -365,6 +366,12 @@ struct ConstEval
                if (sig.is_fully_const())
                        return true;
 
+               if (defaultval != RTLIL::State::Sm) {
+                       for (auto &bit : sig)
+                               if (bit.wire) bit = defaultval;
+                       return true;
+               }
+
                for (auto &c : sig.chunks())
                        if (c.wire != NULL)
                                undef.append(c);