radv: add radv_emit_shader_pointer() helper
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 17 May 2018 12:08:43 +0000 (14:08 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 17 May 2018 19:28:59 +0000 (21:28 +0200)
For future work (support for 32-bit GPU pointers).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_cmd_buffer.c
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_private.h

index 1ca687494a413a1077b31e7df701bd00dd81bf4a..a8359ac092fc511715ac0bf2e620832aba9575d7 100644 (file)
@@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
                return;
        assert(loc->num_sgprs == 2);
        assert(!loc->indirect);
-       radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-       radeon_emit(cmd_buffer->cs, va);
-       radeon_emit(cmd_buffer->cs, va >> 32);
+
+       radv_emit_shader_pointer(cmd_buffer->cs,
+                                base_reg + loc->sgpr_idx * 4, va);
 }
 
 static void
@@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
 
        assert(!desc_set_loc->indirect);
        assert(desc_set_loc->num_sgprs == 2);
-       radeon_set_sh_reg_seq(cmd_buffer->cs,
-                             base_reg + desc_set_loc->sgpr_idx * 4, 2);
-       radeon_emit(cmd_buffer->cs, va);
-       radeon_emit(cmd_buffer->cs, va >> 32);
+
+       radv_emit_shader_pointer(cmd_buffer->cs,
+                                base_reg + desc_set_loc->sgpr_idx * 4, va);
 }
 
 static void
index 7067f5b01dfcc61d0cf6dbfcc6481828cfe899a0..c52b3a591f8c3a9e13844c15390dcf8a70bac8b1 100644 (file)
@@ -1963,9 +1963,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
                                   R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
 
                for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-                       radeon_set_sh_reg_seq(cs, regs[i], 2);
-                       radeon_emit(cs, va);
-                       radeon_emit(cs, va >> 32);
+                       radv_emit_shader_pointer(cs, regs[i], va);
                }
        } else {
                uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1976,9 +1974,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
                                   R_00B530_SPI_SHADER_USER_DATA_LS_0};
 
                for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-                       radeon_set_sh_reg_seq(cs, regs[i], 2);
-                       radeon_emit(cs, va);
-                       radeon_emit(cs, va >> 32);
+                       radv_emit_shader_pointer(cs, regs[i], va);
                }
        }
 }
index 304ed17f01ab31e0fea4bcd29e4f6f06eddcd61d..adfd75c2a8747ea5a0c19db72cd249b7a8446e0f 100644 (file)
@@ -59,6 +59,7 @@
 #include "ac_surface.h"
 #include "radv_descriptor_set.h"
 #include "radv_extensions.h"
+#include "radv_cs.h"
 
 #include <llvm-c/TargetMachine.h>
 
@@ -1128,6 +1129,15 @@ bool radv_get_memory_fd(struct radv_device *device,
                        struct radv_device_memory *memory,
                        int *pFD);
 
+static inline void
+radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+                        uint32_t sh_offset, uint64_t va)
+{
+       radeon_set_sh_reg_seq(cs, sh_offset, 2);
+       radeon_emit(cs, va);
+       radeon_emit(cs, va >> 32);
+}
+
 static inline struct radv_descriptor_state *
 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
                           VkPipelineBindPoint bind_point)