arch-arm: Fix big endian support in do{Long,L1,L2}Descriptor
authorChuan Zhu <chuan.zhu@arm.com>
Wed, 2 Aug 2017 08:52:28 +0000 (09:52 +0100)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Fri, 16 Feb 2018 09:28:24 +0000 (09:28 +0000)
do{Long,L1,L2}Descriptor was not able to load descriptors correctly
for big-endian situations, causing recognised Descriptors.  Added
big-endian related data conversions to correct them.

Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8144
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/table_walker.cc
src/arch/arm/utility.hh

index 428556b1ae7a81825aa55f89254f63f676ea00c3..3c79e43ac423200115acc415e95451d8fbf59e2a 100644 (file)
@@ -1423,6 +1423,9 @@ TableWalker::doL1Descriptor()
         return;
     }
 
+    currState->l1Desc.data = htog(currState->l1Desc.data,
+                                  byteOrder(currState->tc));
+
     DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
             currState->vaddr_tainted, currState->l1Desc.data);
     TlbEntry te;
@@ -1518,6 +1521,9 @@ TableWalker::doLongDescriptor()
         return;
     }
 
+    currState->longDesc.data = htog(currState->longDesc.data,
+                                    byteOrder(currState->tc));
+
     DPRINTF(TLB, "L%d descriptor for %#llx is %#llx (%s)\n",
             currState->longDesc.lookupLevel, currState->vaddr_tainted,
             currState->longDesc.data,
@@ -1709,6 +1715,9 @@ TableWalker::doL2Descriptor()
         return;
     }
 
+    currState->l2Desc.data = htog(currState->l2Desc.data,
+                                  byteOrder(currState->tc));
+
     DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
             currState->vaddr_tainted, currState->l2Desc.data);
     TlbEntry te;
index 8efe4ad109e57d4c70bdccbd916ad009f1a1902e..796ded7713aa209ab4378edc40e327b0b60fa221 100644 (file)
@@ -348,6 +348,11 @@ int decodePhysAddrRange64(uint8_t pa_enc);
  */
 uint8_t encodePhysAddrRange64(int pa_size);
 
+inline ByteOrder byteOrder(ThreadContext *tc)
+{
+    return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
+};
+
 }
 
 #endif