write_verilog: add a missing newline.

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f9207f987efd7f9324727d405ce90218acb..850abfad77c5110c5e310e33de6bef0dd517f197 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1419,7 +1419,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
                log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
                                "can't always be mapped directly to Verilog always blocks. Unintended\n"
                                "changes in simulation behavior are possible! Use \"proc\" to convert\n"
-                               "processes to logic networks and registers.", log_id(module));
+                               "processes to logic networks and registers.\n", log_id(module));
 
        f << stringf("\n");
        for (auto it = module->processes.begin(); it != module->processes.end(); ++it)