correct the bitmanip pseudocode to remove spaces from instruction declarations

ternlogi RT,RA,RB,TLI not ternlog RT,   RA,     RB,     TLI

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index d1521a762d1302f8a3c9502760d76fda8f711044..d5b9dddb2cb9a5fbf4defc13127ccc5fb20f1454 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -5,8 +5,8 @@
 
 TLI-Form
 
-* ternlogi RT, RA, RB, TLI
-* ternlogi. RT, RA, RB, TLI
+* ternlogi RT,RA,RB,TLI
+* ternlogi. RT,RA,RB,TLI
 
 Pseudo-code:
 
@@ -24,8 +24,8 @@ Special Registers Altered:
 
 X-Form
 
-* grev RT, RA, RB (Rc=0)
-* grev. RT, RA, RB (Rc=1)
+* grev RT,RA,RB (Rc=0)
+* grev. RT,RA,RB (Rc=1)
 
 Pseudo-code:
 
@@ -44,8 +44,8 @@ Special Registers Altered:
 
 XB-Form
 
-* grevi RT, RA, XBI (Rc=0)
-* grevi. RT, RA, XBI (Rc=1)
+* grevi RT,RA,XBI (Rc=0)
+* grevi. RT,RA,XBI (Rc=1)
 
 Pseudo-code:
 
@@ -63,8 +63,8 @@ Special Registers Altered:
 
 X-Form
 
-* grevw RT, RA, RB (Rc=0)
-* grevw. RT, RA, RB (Rc=1)
+* grevw RT,RA,RB (Rc=0)
+* grevw. RT,RA,RB (Rc=1)
 
 Pseudo-code:
 
@@ -84,8 +84,8 @@ Special Registers Altered:
 
 X-Form
 
-* grevwi RT, RA, SH (Rc=0)
-* grevwi. RT, RA, SH (Rc=1)
+* grevwi RT,RA,SH (Rc=0)
+* grevwi. RT,RA,SH (Rc=1)
 
 Pseudo-code: