examples/two_dividers: demonstrate InsertCE and InsertReset decorators

diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
index 98759419cbffe9c914367e7bdd50e3c7c58ac273..723522042f3b9edbfc6996e5ad58733aeefc4715 100644 (file)
--- a/examples/basic/two_dividers.py
+++ b/examples/basic/two_dividers.py
@@ -2,14 +2,16 @@ from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
 class Example(Module):
-       def __init__(self):
-               d1 = divider.Divider(16)
-               d2 = divider.Divider(16)
+       def __init__(self, width):
+               d1 = divider.Divider(width)
+               d2 = divider.Divider(width)
                self.submodules += d1, d2
                self.ios = {
                        d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
                        d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
 
-example = Example()
-print(verilog.convert(example, example.ios))
+example = Example(16)
+print(verilog.convert(example, example.ios | {example.ce, example.reset}))