[sim, xcc] changed cvt/trunc to use GPRs for int args

this way, we don't have to futz with storing integers in recoded
floating-point registers.  too bad we lose some decoupling.

diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 5faac2a4691fceba6698cfef188a2f3a691ca4a5..8a60e643ca7160a6ffd6728b202f8750c9aeaa33 100644 (file)
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = i64_to_f64(FRS1);
+FRDR = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
index 67bc7986abe267a407f30ed591d70f9dc80b1427..96acc2b53e920ff2598050166de90a3d7a76ca4a 100644 (file)
--- a/riscv/insns/cvt_d_w.h
+++ b/riscv/insns/cvt_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = i32_to_f64(FRS1);
+FRDR = i32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index f5332f9cf716e87df32ab414eede927f930ede22..fe10e85c3ec231467ff204b3859e1e78d3e42212 100644 (file)
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = i64_to_f32(FRS1);
+FRDR = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index 9db538636f045477a43354984739cb6a3a7802d4..8501547f3415f6cfb66dbdae2ee25837ec7e6ab5 100644 (file)
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = i32_to_f32(FRS1);
+FRDR = i32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 5faac2a4691fceba6698cfef188a2f3a691ca4a5..8a60e643ca7160a6ffd6728b202f8750c9aeaa33 100644 (file)
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = i64_to_f64(FRS1);
+FRDR = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
index 1b35e06d572a65bef79380a971261398cc03d948..494f9b0bf924a5c219891a271a6210adc57f42d7 100644 (file)
--- a/riscv/insns/cvtu_d_w.h
+++ b/riscv/insns/cvtu_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = ui32_to_f64(FRS1);
+FRDR = ui32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index f5332f9cf716e87df32ab414eede927f930ede22..fe10e85c3ec231467ff204b3859e1e78d3e42212 100644 (file)
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = i64_to_f32(FRS1);
+FRDR = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index 252e0cc010fba887dc0aff86ef306fd33c9a6055..fb76e6d7490a3b910b8d709f77fc5c7d790c9fd5 100644 (file)
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = ui32_to_f32(FRS1);
+FRDR = ui32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_l_d.h b/riscv/insns/trunc_l_d.h
index e71957bfdf4b9b584edd67f29488b55768129823..63af055cbcfaf684182b11ee9c27ef289aa13fb7 100644 (file)
--- a/riscv/insns/trunc_l_d.h
+++ b/riscv/insns/trunc_l_d.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = f64_to_i64_r_minMag(FRS1,true);
+RDR = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_l_s.h b/riscv/insns/trunc_l_s.h
index 1d48192162e191541c673f91ebe0c41e4eeb2dad..03c114aa93dee27cb41eae6ec8b4b47ba7332be9 100644 (file)
--- a/riscv/insns/trunc_l_s.h
+++ b/riscv/insns/trunc_l_s.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = f32_to_i64_r_minMag(FRS1,true);
+RDR = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_w_d.h b/riscv/insns/trunc_w_d.h
index 2fea3dcadf656b075e21a50ad0071ffcc81065b5..5f874aacff9c060dfaac3140683013dcf23dabb9 100644 (file)
--- a/riscv/insns/trunc_w_d.h
+++ b/riscv/insns/trunc_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_to_i32_r_minMag(FRS1,true);
+RDR = f64_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_w_s.h b/riscv/insns/trunc_w_s.h
index e70f9c4795c1009289198b111965db50351ebaf4..42be7535d3c5ac368bb68367c61866cdaa56aeda 100644 (file)
--- a/riscv/insns/trunc_w_s.h
+++ b/riscv/insns/trunc_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_to_i32_r_minMag(FRS1,true);
+RDR = f32_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_l_d.h b/riscv/insns/truncu_l_d.h
index e71957bfdf4b9b584edd67f29488b55768129823..63af055cbcfaf684182b11ee9c27ef289aa13fb7 100644 (file)
--- a/riscv/insns/truncu_l_d.h
+++ b/riscv/insns/truncu_l_d.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = f64_to_i64_r_minMag(FRS1,true);
+RDR = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_l_s.h b/riscv/insns/truncu_l_s.h
index 1d48192162e191541c673f91ebe0c41e4eeb2dad..03c114aa93dee27cb41eae6ec8b4b47ba7332be9 100644 (file)
--- a/riscv/insns/truncu_l_s.h
+++ b/riscv/insns/truncu_l_s.h
@@ -1,3 +1,4 @@
+require64;
 require_fp;
-FRDR = f32_to_i64_r_minMag(FRS1,true);
+RDR = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_w_d.h b/riscv/insns/truncu_w_d.h
index bb674f6af2a85d1ff69c3a23a7ced1e40f9b4308..4187e530fcee433ef9fcaa28ed877e7511975392 100644 (file)
--- a/riscv/insns/truncu_w_d.h
+++ b/riscv/insns/truncu_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_to_ui32_r_minMag(FRS1,true);
+RDR = f64_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_w_s.h b/riscv/insns/truncu_w_s.h
index d85f9e5a93562708b6e33e2f979a91344b3de375..2014c2bd003d2d8710c3cb79c59261e61c06a4f5 100644 (file)
--- a/riscv/insns/truncu_w_s.h
+++ b/riscv/insns/truncu_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_to_ui32_r_minMag(FRS1,true);
+RDR = f32_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;