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diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 0543db6b476f9cc7d1aac1218194bf109add656c..7ba8f755784778db28b15e34473583ee8683aba0 100644 (file)
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -21,9 +21,10 @@
 
 ```
     Book I Scalar Floating-Point 4.6.2.1
-    Appendix D Power ISA sorted by opcode
-    Appendix E Power ISA sorted by version
-    Appendix F Power ISA sorted by mnemonic
+    Appendix E Power ISA sorted by opcode
+    Appendix F Power ISA sorted by version
+    Appendix G Power ISA sorted by Compliancy Subset
+    Appendix H Power ISA sorted by mnemonic
 ```
 
 **Summary**
@@ -86,9 +87,10 @@ Book I as a new Section 4.6.2.1
 
 # Appendices
 
-    Appendix D Power ISA sorted by opcode
-    Appendix E Power ISA sorted by version
-    Appendix F Power ISA sorted by mnemonic
+    Appendix E Power ISA sorted by opcode
+    Appendix F Power ISA sorted by version
+    Appendix G Power ISA sorted by Compliancy Subset
+    Appendix H Power ISA sorted by mnemonic
 
 | Form | Book | Page | Version | mnemonic | Description |
 |------|------|------|---------|----------|-------------|
@@ -108,9 +110,9 @@ Book I as a new Section 4.6.2.1
 Pseudocode:
 
 ```
-    bf16 <- d0 || d1 || d2 # create BF16 immediate
-    fp32 <- bf16 || [0]*16 # convert BF16 to FP32
-    FRT <- DOUBLE(fp32)    # convert FP32 to FP64
+    bf16 <- d0 || d1 || d2 # create bfloat16 immediate
+    fp32 <- bf16 || [0]*16 # convert bfloat16 to BFP32
+    FRT <- DOUBLE(fp32)    # convert BFP32 to BFP64
 ```
 
 Special registers altered:
@@ -148,9 +150,9 @@ Pseudocode:
 
 ```
     n <- (FRT)                     # read FRT
-    fp32 <- SINGLE(n)              # convert to FP32
+    fp32 <- SINGLE(n)              # convert to BFP32
     fp32[16:31] <- d0 || d1 || d2  # replace LSB half
-    FRT <- DOUBLE(fp32)            # convert back to FP64
+    FRT <- DOUBLE(fp32)            # convert back to BFP64
 ```
 
 Special registers altered:
@@ -168,18 +170,18 @@ Programmer's note:
 The use of these two instructions is strategically similar to
 how `li` combined with `oris` may be used to construct 32-bit Integers.
 If a prior `fmvis` instruction had been used to
-set the upper 16-bits from an FP32 value, `fishmv` may be used
+set the upper 16-bits from a BFP32 value, `fishmv` may be used
 to set the
 lower 16-bits.
 Example:
 
 ```
     # these two combined instructions write 0x3f808000
-    # into f4 as an FP32 to be converted to an FP64.
+    # into f4 as a BFP32 to be converted to a BFP64.
     # actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
     # first the upper bits, happens to be +1.0
     fmvis f4, 0x3F80 # writes +1.0 to f4
-    # now write the lower 16 bits of an FP32
+    # now write the lower 16 bits of a BFP32
     fishmv f4, 0x8000 # writes +1.00390625 to f4
 ```
 [[!tag opf_rfc]]