* simops.c: Fix "mov imm8,an" and "mov imm16,dn".

Fixes 80 or so c-torture execution failures.  400 to go.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index f191d1594587f9253ee40c7ee4f0963c6dc2a9bb..7695f4fc7d9c06c3c0a584258e129fde1b69d450 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,7 @@
+Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
+
 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 
        * simops.c: Fix overflow computation for many instructions.

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index abb5b0cd56295da0a35729e391879fd1680f8007..217cd16101c8009e8030e2106d9b3461eaf32d7c 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -89,7 +89,7 @@ void OP_F1D0 ()
 /* mov imm8, an */
 void OP_9000 ()
 {
-  State.regs[REG_D0 + ((insn & 0x300) >> 8)] = insn & 0xff;
+  State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
 }
 
 /* mov am, an */
@@ -445,7 +445,7 @@ void OP_2C0000 ()
   unsigned long value;
 
   value = SEXT16 (insn & 0xffff);
-  State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
+  State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
 }
 
 /* mov imm32,dn */