fix indentation across files

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 9c360efb6a68e0e8536dcac5aa192796f3e65fd5..9631525888a5c08cf797452c01435fc93ec2c7b5 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -51,7 +51,7 @@ namespace AST_INTERNAL {
        std::map<std::string, AstNode*> current_scope;
        const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
        RTLIL::SigSpec ignoreThisSignalsInInitial;
-    std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
+       std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
        AstNode *current_always, *current_top_block, *current_block, *current_block_child;
        AstModule *current_module;
        bool current_always_clocked;
@@ -195,6 +195,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
        is_logic = false;
        is_signed = false;
        is_string = false;
+       is_wand = false;
+       is_wor = false;
        was_checked = false;
        range_valid = false;
        range_swapped = false;
@@ -941,7 +943,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
                log("--- END OF AST DUMP ---\n");
        }
 
-    wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
+       wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
 
        if (!defer)
        {

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 7b1744b2e69c3efd00dd4425a5fc91f5bd01fcb7..c2a7744c4b8d063ac067af88566e6de501de2c37 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -327,7 +327,7 @@ namespace AST_INTERNAL
        extern std::map<std::string, AST::AstNode*> current_scope;
        extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
        extern RTLIL::SigSpec ignoreThisSignalsInInitial;
-    extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
+       extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
        extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
        extern AST::AstModule *current_module;
        extern bool current_always_clocked;

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index c60f8f5cc5a7ca1534075ea533a1cf9049a9c90a..7a6a2be6b4276458038cb547cf16cd4e2808948c 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -166,37 +166,37 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 // helper function for creating RTLIL code for wand/wor declarations
 static void wandwor2rtlil(AstNode *that, RTLIL::Wire *output_wire, bool gen_attributes = true)
 {
-    std::string type;
-
-    if (that->is_wand) {
-        type = "$reduce_and";
-    } else if (that->is_wor) {
-        type = "$reduce_or";
-    } else {
-        log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n");
-    }
+       std::string type;
+
+       if (that->is_wand) {
+               type = "$reduce_and";
+       } else if (that->is_wor) {
+               type = "$reduce_or";
+       } else {
+               log_file_error(that->filename, that->linenum, "Unrecognized wired logic type.\n");
+       }
 
        std::stringstream sstr;
        sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
 
        RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
        cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
-       
+
        if (gen_attributes)
                for (auto &attr : that->attributes) {
                        if (attr.second->type != AST_CONSTANT)
                                log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
                        cell->attributes[attr.first] = attr.second->asAttrConst();
                }
-    
+
        cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
        cell->parameters["\\A_WIDTH"] = RTLIL::Const(0);
        cell->setPort("\\A", RTLIL::SigSpec());
-    
+
        cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
        cell->setPort("\\Y", output_wire);
-                
-    wire_logic_map[output_wire] = cell;
+
+       wire_logic_map[output_wire] = cell;
 }
 
 // helper class for converting AST always nodes to RTLIL processes
@@ -956,12 +956,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                wire->attributes[attr.first] = attr.second->asAttrConst();
                        }
 
-            if (is_wand || is_wor) {
-                if (wire->width > 1)
-                    log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n");
-                wandwor2rtlil(this, wire);
-            }
-
+                       if (is_wand || is_wor) {
+                               if (wire->width > 1)
+                                       log_file_error(filename, linenum, "Multi-bit wand/wor not supported.\n");
+                               wandwor2rtlil(this, wire);
+                       }
                }
                break;
 
@@ -1493,45 +1492,44 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        // add entries to current_module->connections for assignments (outside of always blocks)
        case AST_ASSIGN:
                {
-            bool left_had_const = false;
+                       bool left_had_const = false;
                        RTLIL::SigSpec left = children[0]->genRTLIL();
                        RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
 
-            RTLIL::SigSpec new_left, new_right;
-            for (int i = 0; i < GetSize(left); i++)
-                if (left[i].wire) {
-                    std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(left[i].wire);
-                    if (iter == wire_logic_map.end())
-                    {
-                        new_left.append(left[i]);
-                    } else {
-                        RTLIL::Cell *reduce_cell = iter->second;
-                        RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
-                        int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
-                        log_warning("%d\n", reduce_cell_in.size());
-
-                        RTLIL::Wire *new_reduce_input = current_module->addWire(
-                                stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
-                        new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
-                        reduce_cell_in.append(new_reduce_input);
-                           reduce_cell->setPort("\\A", reduce_cell_in);
-                        reduce_cell->fixup_parameters();
-                        new_left.append(new_reduce_input);
-                    }
-                    new_right.append(right[i]);
-                } else {
-                    left_had_const = true;
-                }
-
-            left = new_left;
-            right = new_right;
+                       RTLIL::SigSpec new_left, new_right;
+                       for (int i = 0; i < GetSize(left); i++)
+                               if (left[i].wire) {
+                                       std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(left[i].wire);
+                                       if (iter == wire_logic_map.end())
+                                       {
+                                               new_left.append(left[i]);
+                                       } else {
+                                               RTLIL::Cell *reduce_cell = iter->second;
+                                               RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
+                                               int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
+
+                                               RTLIL::Wire *new_reduce_input = current_module->addWire(
+                                                               stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
+                                               new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+                                               reduce_cell_in.append(new_reduce_input);
+                                               reduce_cell->setPort("\\A", reduce_cell_in);
+                                               reduce_cell->fixup_parameters();
+                                               new_left.append(new_reduce_input);
+                                       }
+                                       new_right.append(right[i]);
+                               } else {
+                                       left_had_const = true;
+                               }
+
+                       left = new_left;
+                       right = new_right;
                        current_module->connect(RTLIL::SigSig(left, right));
-            
-            if (left_had_const)
-                log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
-                        "    old assignment: %s = %s\n    new assignment: %s = %s.\n",
-                        log_signal(left), log_signal(right),
-                        log_signal(new_left), log_signal(new_right));
+
+                       if (left_had_const)
+                               log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
+                                               "    old assignment: %s = %s\n    new assignment: %s = %s.\n",
+                                               log_signal(left), log_signal(right),
+                                               log_signal(new_left), log_signal(new_right));
                }
                break;
 
@@ -1576,14 +1574,34 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                }
                                if (child->type == AST_ARGUMENT) {
                                        RTLIL::SigSpec sig;
-                                       if (child->children.size() > 0)
+                                       RTLIL::SigSpec new_sig;
+                                       if (child->children.size() > 0) {
                                                sig = child->children[0]->genRTLIL();
+                                               for (int i = 0; i < GetSize(sig); i++) {
+                                                       std::map<RTLIL::SigSpec, RTLIL::Cell*>::iterator iter = wire_logic_map.find(sig[i].wire);
+                                                       if (iter == wire_logic_map.end()) {
+                                                               new_sig.append(sig[i]);
+                                                       } else {
+                                                               RTLIL::Cell *reduce_cell = iter->second;
+                                                               RTLIL::SigSpec reduce_cell_in = reduce_cell->getPort("\\A");
+                                                               int reduce_width = reduce_cell->getParam("\\A_WIDTH").as_int();
+
+                                                               RTLIL::Wire *new_reduce_input = current_module->addWire(
+                                                                               stringf("%s_in%d", reduce_cell->name.c_str(), reduce_width));
+                                                               new_reduce_input->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+                                                               reduce_cell_in.append(new_reduce_input);
+                                                               reduce_cell->setPort("\\A", reduce_cell_in);
+                                                               reduce_cell->fixup_parameters();
+                                                               new_sig.append(new_reduce_input);
+                                                       }
+                                               }
+                                       }
                                        if (child->str.size() == 0) {
                                                char buf[100];
                                                snprintf(buf, 100, "$%d", ++port_counter);
-                                               cell->setPort(buf, sig);
+                                               cell->setPort(buf, new_sig);
                                        } else {
-                                               cell->setPort(child->str, sig);
+                                               cell->setPort(child->str, new_sig);
                                        }
                                        continue;
                                }

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8800705acccb1f42cca09d468bdf474441f630df..8244a8f444d231e174a64eeda3094699c7a9595a 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -486,10 +486,10 @@ wire_type_token:
        TOK_WIRE {
        } |
        TOK_WOR {
-        astbuf3->is_wor = true;
+               astbuf3->is_wor = true;
        } |
        TOK_WAND {
-        astbuf3->is_wand = true;
+               astbuf3->is_wand = true;
        } |
        TOK_REG {
                astbuf3->is_reg = true;