bzip2 is a tru64 regression, not linux
authorGabe Black <gblack@eecs.umich.edu>
Sun, 11 Mar 2007 23:08:38 +0000 (19:08 -0400)
committerGabe Black <gblack@eecs.umich.edu>
Sun, 11 Mar 2007 23:08:38 +0000 (19:08 -0400)
--HG--
rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out
rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr
rename : tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out
rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr
rename : tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
rename : tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
extra : convert_revision : c3f5f5b73186cf6e72c1c8418583d3300e04ad8a

30 files changed:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini [deleted file]
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out [deleted file]
tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt [deleted file]
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr [deleted file]
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr [deleted file]
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout [deleted file]
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr [new file with mode: 0644]
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout [new file with mode: 0644]

diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
deleted file mode 100644 (file)
index 9ae6265..0000000
+++ /dev/null
@@ -1,419 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
deleted file mode 100644 (file)
index 690cc57..0000000
+++ /dev/null
@@ -1,405 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
deleted file mode 100644 (file)
index bc68665..0000000
+++ /dev/null
@@ -1,417 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                   1060300638                       # Number of BTB hits
-global.BPredUnit.BTBLookups                1075264664                       # Number of BTB lookups
-global.BPredUnit.RASInCorrect                     132                       # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect               20658855                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted             1028649695                       # Number of conditional branches predicted
-global.BPredUnit.lookups                   1098978166                       # Number of BP lookups
-global.BPredUnit.usedRAS                     20738311                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  28281                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1256892                       # Number of bytes of host memory used
-host_seconds                                 61385.49                       # Real time elapsed on the host
-host_tick_rate                                 405833                       # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads          114920109                       # Number of conflicting loads.
-memdepunit.memDep.conflictingStores          60881817                       # Number of conflicting stores.
-memdepunit.memDep.insertedLoads             938731548                       # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores            389309694                       # Number of stores inserted to the mem dependence unit.
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1736043781                       # Number of instructions simulated
-sim_seconds                                  0.024912                       # Number of seconds simulated
-sim_ticks                                 24912272090                       # Number of ticks simulated
-system.cpu.commit.COM:branches              214632552                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          72343657                       # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples   5678957793                      
-system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0   5103057521   8985.90%           
-                               1    193842571    341.33%           
-                               2    126727829    223.15%           
-                               3     63255233    111.39%           
-                               4     47590442     83.80%           
-                               5     34302037     60.40%           
-                               6     22774532     40.10%           
-                               7     15063971     26.53%           
-                               8     72343657    127.39%           
-system.cpu.commit.COM:committed_per_cycle.max_value            8                      
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count                1819780126                       # Number of instructions committed
-system.cpu.commit.COM:loads                 445666361                       # Number of loads committed
-system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  606571343                       # Number of memory references committed
-system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          20658355                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts      3012390712                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
-system.cpu.cpi                              14.350025                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        14.350025                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          466176479                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  5764.172372                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  5678.042412                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              454097633                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    69624550394                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.025910                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses             12078846                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits           4784670                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  41416640690                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.015647                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7294176                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             157574910                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   35156809407                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.019621                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             3153592                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1270515                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  26783900812                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011716                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1883077                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs   972.020892                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets  2881.979981                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  66.650940                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs             659829                       # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets           896062                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs    641367573                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets   2582432746                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           626904981                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  6878.830546                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  7431.476663                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               611672543                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    104781359801                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.024298                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses              15232438                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            6055185                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  68200541502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.014639                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9177253                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          626904981                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  6878.830546                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  7431.476663                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              611672543                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   104781359801                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.024298                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses             15232438                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           6055185                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  68200541502                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.014639                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9177253                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                9173157                       # number of replacements
-system.cpu.dcache.sampled_refs                9177253                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4093.061614                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                611672543                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               39716000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2244715                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles     3168036062                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            511                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      48557069                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      6641345328                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles        1298412925                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles         1202046298                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       501929792                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           1629                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles       10462509                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                  1098978166                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 541280485                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                    1955627258                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes              11328270                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     7938391391                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles               242391708                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.177803                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          541280485                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches         1081038949                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.284345                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples          6180887586                      
-system.cpu.fetch.rateDist.min_value                 0                      
-                               0   4766540797   7711.74%           
-                               1     80764415    130.67%           
-                               2     63598055    102.89%           
-                               3     58203597     94.17%           
-                               4    424384465    686.61%           
-                               5     69131012    111.85%           
-                               6     94422767    152.77%           
-                               7     44649271     72.24%           
-                               8    579193207    937.07%           
-system.cpu.fetch.rateDist.max_value                 8                      
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses          541280484                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  5378.819380                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  4616.750831                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              541279194                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        6938677                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1290                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               387                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency      4168926                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             903                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets  4207.523810                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               599423.249169                       # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets               21                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets        88358                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           541280484                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  5378.819380                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  4616.750831                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               541279194                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         6938677                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000002                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1290                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                387                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      4168926                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              903                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses          541280484                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  5378.819380                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  4616.750831                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              541279194                       # number of overall hits
-system.cpu.icache.overall_miss_latency        6938677                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000002                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1290                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               387                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      4168926                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             903                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.sampled_refs                    903                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                716.132429                       # Cycle average of tags in use
-system.cpu.icache.total_refs                541279194                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                     18731384505                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                250098653                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     147895912                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.440971                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    918923683                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  177016651                       # Number of stores executed
-system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1839076786                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2471794731                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.797100                       # average fanout of values written-back
-system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1465928228                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.399909                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2475054397                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             21956654                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles              2471410228                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             938731548                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 45                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts         111073783                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            389309694                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          4831881465                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             741907032                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts         286170200                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            2725595031                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                1536928                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                161620                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              501929792                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles               6153373                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            8                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked    233590575                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        41593346                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses       516978                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        47985                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads            8                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads    493065187                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores    228404712                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          47985                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       726441                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       21230213                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.069686                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.069686                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0              3011765231                       # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
-                          (null)            0      0.00%            # Type of FU issued
-                          IntAlu   1970711875     65.43%            # Type of FU issued
-                         IntMult          679      0.00%            # Type of FU issued
-                          IntDiv            0      0.00%            # Type of FU issued
-                        FloatAdd          206      0.00%            # Type of FU issued
-                        FloatCmp           15      0.00%            # Type of FU issued
-                        FloatCvt          146      0.00%            # Type of FU issued
-                       FloatMult           12      0.00%            # Type of FU issued
-                        FloatDiv           24      0.00%            # Type of FU issued
-                       FloatSqrt            0      0.00%            # Type of FU issued
-                         MemRead    862446019     28.64%            # Type of FU issued
-                        MemWrite    178606255      5.93%            # Type of FU issued
-                       IprAccess            0      0.00%            # Type of FU issued
-                    InstPrefetch            0      0.00%            # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt              11307551                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.003754                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
-                          (null)            0      0.00%            # attempts to use FU when none available
-                          IntAlu       509990      4.51%            # attempts to use FU when none available
-                         IntMult            0      0.00%            # attempts to use FU when none available
-                          IntDiv            0      0.00%            # attempts to use FU when none available
-                        FloatAdd            0      0.00%            # attempts to use FU when none available
-                        FloatCmp            0      0.00%            # attempts to use FU when none available
-                        FloatCvt            0      0.00%            # attempts to use FU when none available
-                       FloatMult            0      0.00%            # attempts to use FU when none available
-                        FloatDiv            0      0.00%            # attempts to use FU when none available
-                       FloatSqrt            0      0.00%            # attempts to use FU when none available
-                         MemRead      9173598     81.13%            # attempts to use FU when none available
-                        MemWrite      1623963     14.36%            # attempts to use FU when none available
-                       IprAccess            0      0.00%            # attempts to use FU when none available
-                    InstPrefetch            0      0.00%            # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples   6180887586                      
-system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0   4878979324   7893.65%           
-                               1    360055339    582.53%           
-                               2    481197713    778.53%           
-                               3    280796976    454.30%           
-                               4     94854448    153.46%           
-                               5     50760526     82.12%           
-                               6     26723872     43.24%           
-                               7      6795220     10.99%           
-                               8       724168      1.17%           
-system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate                     0.487271                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                 4683985508                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                3011765231                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  45                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined      2916477755                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           6096386                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   3050829124                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses           9178154                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  7336.712513                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2076.036854                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               7008989                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   15914539999                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.236340                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             2169165                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4503266483                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.236340                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        2169165                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         2244715                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             2215400                       # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate       0.013060                       # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses             29315                       # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate     0.013060                       # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses        29315                       # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.252507                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9178154                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  7336.712513                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  2076.036854                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                7008989                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    15914539999                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.236340                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2169165                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   4503266483                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.236340                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2169165                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses          11422869                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  7238.883228                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  2076.036854                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               9224389                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   15914539999                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.192463                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2198480                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   4503266483                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.189897                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2169165                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements               2136397                       # number of replacements
-system.cpu.l2cache.sampled_refs               2169165                       # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32623.472165                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 9224389                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle             520424000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1039341                       # number of writebacks
-system.cpu.numCycles                       6180887586                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles       2894504060                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         6511750                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles        1451413065                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents      266047107                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents        3125053                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     8501370508                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      6112671585                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   4584914520                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles         1056218413                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       501929792                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles      276756270                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps        3208711557                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles        65986                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           49                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts         1117979447                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           47                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                         7293390                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
deleted file mode 100644 (file)
index cdd59ed..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7006
-warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
deleted file mode 100644 (file)
index 0c5c001..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
deleted file mode 100644 (file)
index ad57a52..0000000
+++ /dev/null
@@ -1,113 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
deleted file mode 100644 (file)
index 891519c..0000000
+++ /dev/null
@@ -1,107 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
deleted file mode 100644 (file)
index 7422e3a..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate                                 927424                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 144704                       # Number of bytes of host memory used
-host_seconds                                  1962.19                       # Real time elapsed on the host
-host_tick_rate                                 927424                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1819780129                       # Number of instructions simulated
-sim_seconds                                  0.001820                       # Number of seconds simulated
-sim_ticks                                  1819780128                       # Number of ticks simulated
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1819780129                       # number of cpu cycles simulated
-system.cpu.num_insts                       1819780129                       # Number of instructions executed
-system.cpu.num_refs                         606571345                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
deleted file mode 100644 (file)
index 87866a2..0000000
+++ /dev/null
@@ -1 +0,0 @@
-warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
deleted file mode 100644 (file)
index 0c5c001..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
deleted file mode 100644 (file)
index 0a123d4..0000000
+++ /dev/null
@@ -1,236 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
deleted file mode 100644 (file)
index 4692c5d..0000000
+++ /dev/null
@@ -1,228 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
deleted file mode 100644 (file)
index 45b7beb..0000000
+++ /dev/null
@@ -1,220 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate                                 486900                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1198232                       # Number of bytes of host memory used
-host_seconds                                  3737.50                       # Real time elapsed on the host
-host_tick_rate                                8500130                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1819780129                       # Number of instructions simulated
-sim_seconds                                  0.031769                       # Number of seconds simulated
-sim_ticks                                 31769223012                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3121.340330                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2121.340330                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    22543612099                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  15321198099                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3602.533807                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2602.533807                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    6806339173                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   4917019173                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3221.115901                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2221.115901                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     29349951272                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  20238217272                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3221.115901                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2221.115901                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              596212431                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    29349951272                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9111734                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  20238217272                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                9107638                       # number of replacements
-system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4091.845274                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               75264000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2244708                       # number of writebacks
-system.cpu.icache.ReadReq_accesses         1819780130                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  4089.753117                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  3089.753117                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1819779328                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        3279982                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                  802                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency      2477982                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             802                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               2269051.531172                       # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1819780130                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  4089.753117                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  3089.753117                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1819779328                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         3279982                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                   802                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      2477982                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              802                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses         1819780130                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  4089.753117                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  3089.753117                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1819779328                       # number of overall hits
-system.cpu.icache.overall_miss_latency        3279982                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                  802                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      2477982                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             802                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                625.996248                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1819779328                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses           9112536                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  3215.890455                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1919.394872                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               6952383                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    6946815413                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.237053                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             2160153                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4146186590                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.237053                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        2160153                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses      2244708                       # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits      2215611                       # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate     0.012962                       # miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_misses        29097                       # number of WriteReqNoAck|Writeback misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate     0.012962                       # mshr miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses        29097                       # number of WriteReqNoAck|Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.244141                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  3215.890455                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1919.394872                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                6952383                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     6946815413                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.237053                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              2160153                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   4146186590                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.237053                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         2160153                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses          11357244                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  3173.148527                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1919.394872                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               9167994                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    6946815413                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.192762                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             2189250                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   4146186590                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.190200                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        2160153                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements               2127385                       # number of replacements
-system.cpu.l2cache.sampled_refs               2160153                       # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32563.117941                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 9167994                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle             748591000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1038202                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                      31769223012                       # number of cpu cycles simulated
-system.cpu.num_insts                       1819780129                       # Number of instructions executed
-system.cpu.num_refs                         606571345                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
deleted file mode 100644 (file)
index 87866a2..0000000
+++ /dev/null
@@ -1 +0,0 @@
-warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
deleted file mode 100644 (file)
index 0c5c001..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644 (file)
index 0000000..9ae6265
--- /dev/null
@@ -0,0 +1,419 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out
new file mode 100644 (file)
index 0000000..690cc57
--- /dev/null
@@ -0,0 +1,405 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+phase=0
+numThreads=1
+activity=0
+workload=system.cpu.workload
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
new file mode 100644 (file)
index 0000000..bc68665
--- /dev/null
@@ -0,0 +1,417 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits                   1060300638                       # Number of BTB hits
+global.BPredUnit.BTBLookups                1075264664                       # Number of BTB lookups
+global.BPredUnit.RASInCorrect                     132                       # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect               20658855                       # Number of conditional branches incorrect
+global.BPredUnit.condPredicted             1028649695                       # Number of conditional branches predicted
+global.BPredUnit.lookups                   1098978166                       # Number of BP lookups
+global.BPredUnit.usedRAS                     20738311                       # Number of times the RAS was used to get a target.
+host_inst_rate                                  28281                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1256892                       # Number of bytes of host memory used
+host_seconds                                 61385.49                       # Real time elapsed on the host
+host_tick_rate                                 405833                       # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads          114920109                       # Number of conflicting loads.
+memdepunit.memDep.conflictingStores          60881817                       # Number of conflicting stores.
+memdepunit.memDep.insertedLoads             938731548                       # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores            389309694                       # Number of stores inserted to the mem dependence unit.
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                  1736043781                       # Number of instructions simulated
+sim_seconds                                  0.024912                       # Number of seconds simulated
+sim_ticks                                 24912272090                       # Number of ticks simulated
+system.cpu.commit.COM:branches              214632552                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events          72343657                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples   5678957793                      
+system.cpu.commit.COM:committed_per_cycle.min_value            0                      
+                               0   5103057521   8985.90%           
+                               1    193842571    341.33%           
+                               2    126727829    223.15%           
+                               3     63255233    111.39%           
+                               4     47590442     83.80%           
+                               5     34302037     60.40%           
+                               6     22774532     40.10%           
+                               7     15063971     26.53%           
+                               8     72343657    127.39%           
+system.cpu.commit.COM:committed_per_cycle.max_value            8                      
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count                1819780126                       # Number of instructions committed
+system.cpu.commit.COM:loads                 445666361                       # Number of loads committed
+system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                  606571343                       # Number of memory references committed
+system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts          20658355                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts      3012390712                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
+system.cpu.cpi                              14.350025                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                        14.350025                       # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses          466176479                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  5764.172372                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  5678.042412                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              454097633                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    69624550394                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.025910                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses             12078846                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits           4784670                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  41416640690                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.015647                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         7294176                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             157574910                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   35156809407                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.019621                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             3153592                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1270515                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency  26783900812                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011716                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1883077                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs   972.020892                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets  2881.979981                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  66.650940                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs             659829                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets           896062                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs    641367573                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets   2582432746                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses           626904981                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  6878.830546                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  7431.476663                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               611672543                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    104781359801                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.024298                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses              15232438                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            6055185                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  68200541502                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.014639                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9177253                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses          626904981                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  6878.830546                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  7431.476663                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits              611672543                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   104781359801                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.024298                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses             15232438                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           6055185                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  68200541502                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.014639                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9177253                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                9173157                       # number of replacements
+system.cpu.dcache.sampled_refs                9177253                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse               4093.061614                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                611672543                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               39716000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  2244715                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles     3168036062                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred            511                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      48557069                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts      6641345328                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles        1298412925                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles         1202046298                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles       501929792                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts           1629                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles       10462509                       # Number of cycles decode is unblocking
+system.cpu.fetch.Branches                  1098978166                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 541280485                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                    1955627258                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes              11328270                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     7938391391                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles               242391708                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.177803                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          541280485                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches         1081038949                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.284345                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples          6180887586                      
+system.cpu.fetch.rateDist.min_value                 0                      
+                               0   4766540797   7711.74%           
+                               1     80764415    130.67%           
+                               2     63598055    102.89%           
+                               3     58203597     94.17%           
+                               4    424384465    686.61%           
+                               5     69131012    111.85%           
+                               6     94422767    152.77%           
+                               7     44649271     72.24%           
+                               8    579193207    937.07%           
+system.cpu.fetch.rateDist.max_value                 8                      
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses          541280484                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  5378.819380                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  4616.750831                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              541279194                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency        6938677                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000002                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 1290                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               387                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency      4168926                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             903                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets  4207.523810                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs               599423.249169                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets               21                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets        88358                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses           541280484                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  5378.819380                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  4616.750831                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               541279194                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency         6938677                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000002                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  1290                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                387                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency      4168926                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              903                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses          541280484                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  5378.819380                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  4616.750831                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits              541279194                       # number of overall hits
+system.cpu.icache.overall_miss_latency        6938677                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000002                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 1290                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               387                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency      4168926                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             903                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                      1                       # number of replacements
+system.cpu.icache.sampled_refs                    903                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                716.132429                       # Cycle average of tags in use
+system.cpu.icache.total_refs                541279194                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idleCycles                     18731384505                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                250098653                       # Number of branches executed
+system.cpu.iew.EXEC:nop                     147895912                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.440971                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    918923683                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  177016651                       # Number of stores executed
+system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
+system.cpu.iew.WB:consumers                1839076786                       # num instructions consuming a value
+system.cpu.iew.WB:count                    2471794731                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.797100                       # average fanout of values written-back
+system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers                1465928228                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.399909                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     2475054397                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             21956654                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles              2471410228                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             938731548                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                 45                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts         111073783                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            389309694                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          4831881465                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             741907032                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts         286170200                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            2725595031                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                1536928                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents                161620                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles              501929792                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles               6153373                       # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads            8                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked    233590575                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads        41593346                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses       516978                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation        47985                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            8                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    493065187                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores    228404712                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          47985                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       726441                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       21230213                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.069686                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.069686                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0              3011765231                       # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+                          (null)            0      0.00%            # Type of FU issued
+                          IntAlu   1970711875     65.43%            # Type of FU issued
+                         IntMult          679      0.00%            # Type of FU issued
+                          IntDiv            0      0.00%            # Type of FU issued
+                        FloatAdd          206      0.00%            # Type of FU issued
+                        FloatCmp           15      0.00%            # Type of FU issued
+                        FloatCvt          146      0.00%            # Type of FU issued
+                       FloatMult           12      0.00%            # Type of FU issued
+                        FloatDiv           24      0.00%            # Type of FU issued
+                       FloatSqrt            0      0.00%            # Type of FU issued
+                         MemRead    862446019     28.64%            # Type of FU issued
+                        MemWrite    178606255      5.93%            # Type of FU issued
+                       IprAccess            0      0.00%            # Type of FU issued
+                    InstPrefetch            0      0.00%            # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt              11307551                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.003754                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+                          (null)            0      0.00%            # attempts to use FU when none available
+                          IntAlu       509990      4.51%            # attempts to use FU when none available
+                         IntMult            0      0.00%            # attempts to use FU when none available
+                          IntDiv            0      0.00%            # attempts to use FU when none available
+                        FloatAdd            0      0.00%            # attempts to use FU when none available
+                        FloatCmp            0      0.00%            # attempts to use FU when none available
+                        FloatCvt            0      0.00%            # attempts to use FU when none available
+                       FloatMult            0      0.00%            # attempts to use FU when none available
+                        FloatDiv            0      0.00%            # attempts to use FU when none available
+                       FloatSqrt            0      0.00%            # attempts to use FU when none available
+                         MemRead      9173598     81.13%            # attempts to use FU when none available
+                        MemWrite      1623963     14.36%            # attempts to use FU when none available
+                       IprAccess            0      0.00%            # attempts to use FU when none available
+                    InstPrefetch            0      0.00%            # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples   6180887586                      
+system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
+                               0   4878979324   7893.65%           
+                               1    360055339    582.53%           
+                               2    481197713    778.53%           
+                               3    280796976    454.30%           
+                               4     94854448    153.46%           
+                               5     50760526     82.12%           
+                               6     26723872     43.24%           
+                               7      6795220     10.99%           
+                               8       724168      1.17%           
+system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate                     0.487271                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                 4683985508                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                3011765231                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                  45                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined      2916477755                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued           6096386                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined   3050829124                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses           9178154                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  7336.712513                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2076.036854                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits               7008989                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   15914539999                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.236340                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             2169165                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4503266483                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.236340                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        2169165                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         2244715                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             2215400                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate       0.013060                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses             29315                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate     0.013060                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses        29315                       # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  4.252507                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses            9178154                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  7336.712513                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  2076.036854                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                7008989                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    15914539999                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.236340                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2169165                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   4503266483                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.236340                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2169165                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses          11422869                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  7238.883228                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  2076.036854                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits               9224389                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   15914539999                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.192463                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2198480                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   4503266483                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.189897                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2169165                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements               2136397                       # number of replacements
+system.cpu.l2cache.sampled_refs               2169165                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse             32623.472165                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 9224389                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle             520424000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1039341                       # number of writebacks
+system.cpu.numCycles                       6180887586                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles       2894504060                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         6511750                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles        1451413065                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents      266047107                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents        3125053                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     8501370508                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      6112671585                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   4584914520                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles         1056218413                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles       501929792                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles      276756270                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps        3208711557                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles        65986                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts           49                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts         1117979447                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts           47                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                         7293390                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr
new file mode 100644 (file)
index 0000000..cdd59ed
--- /dev/null
@@ -0,0 +1,2 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7006
+warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout
new file mode 100644 (file)
index 0000000..0c5c001
--- /dev/null
@@ -0,0 +1,14 @@
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644 (file)
index 0000000..ad57a52
--- /dev/null
@@ -0,0 +1,113 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out
new file mode 100644 (file)
index 0000000..891519c
--- /dev/null
@@ -0,0 +1,107 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
new file mode 100644 (file)
index 0000000..7422e3a
--- /dev/null
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 927424                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 144704                       # Number of bytes of host memory used
+host_seconds                                  1962.19                       # Real time elapsed on the host
+host_tick_rate                                 927424                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                  1819780129                       # Number of instructions simulated
+sim_seconds                                  0.001820                       # Number of seconds simulated
+sim_ticks                                  1819780128                       # Number of ticks simulated
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                       1819780129                       # number of cpu cycles simulated
+system.cpu.num_insts                       1819780129                       # Number of instructions executed
+system.cpu.num_refs                         606571345                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr
new file mode 100644 (file)
index 0000000..87866a2
--- /dev/null
@@ -0,0 +1 @@
+warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout
new file mode 100644 (file)
index 0000000..0c5c001
--- /dev/null
@@ -0,0 +1,14 @@
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644 (file)
index 0000000..0a123d4
--- /dev/null
@@ -0,0 +1,236 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
new file mode 100644 (file)
index 0000000..4692c5d
--- /dev/null
@@ -0,0 +1,228 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
new file mode 100644 (file)
index 0000000..45b7beb
--- /dev/null
@@ -0,0 +1,220 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 486900                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1198232                       # Number of bytes of host memory used
+host_seconds                                  3737.50                       # Real time elapsed on the host
+host_tick_rate                                8500130                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                  1819780129                       # Number of instructions simulated
+sim_seconds                                  0.031769                       # Number of seconds simulated
+sim_ticks                                 31769223012                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  3121.340330                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2121.340330                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    22543612099                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  15321198099                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  3602.533807                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2602.533807                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    6806339173                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   4917019173                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  3221.115901                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2221.115901                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     29349951272                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  20238217272                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  3221.115901                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2221.115901                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits              596212431                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    29349951272                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              9111734                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  20238217272                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                9107638                       # number of replacements
+system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse               4091.845274                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               75264000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  2244708                       # number of writebacks
+system.cpu.icache.ReadReq_accesses         1819780130                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  4089.753117                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  3089.753117                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits             1819779328                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency        3279982                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  802                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency      2477982                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             802                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs               2269051.531172                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses          1819780130                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  4089.753117                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  3089.753117                       # average overall mshr miss latency
+system.cpu.icache.demand_hits              1819779328                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency         3279982                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   802                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency      2477982                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              802                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses         1819780130                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  4089.753117                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  3089.753117                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits             1819779328                       # number of overall hits
+system.cpu.icache.overall_miss_latency        3279982                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  802                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency      2477982                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             802                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                      1                       # number of replacements
+system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                625.996248                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1819779328                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses           9112536                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  3215.890455                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1919.394872                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits               6952383                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    6946815413                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.237053                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             2160153                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4146186590                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.237053                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        2160153                       # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses      2244708                       # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits      2215611                       # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate     0.012962                       # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses        29097                       # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate     0.012962                       # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses        29097                       # number of WriteReqNoAck|Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  4.244141                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  3215.890455                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1919.394872                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                6952383                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     6946815413                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.237053                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2160153                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   4146186590                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.237053                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2160153                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses          11357244                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  3173.148527                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1919.394872                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits               9167994                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    6946815413                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.192762                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2189250                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   4146186590                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.190200                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2160153                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements               2127385                       # number of replacements
+system.cpu.l2cache.sampled_refs               2160153                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse             32563.117941                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 9167994                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle             748591000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1038202                       # number of writebacks
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                      31769223012                       # number of cpu cycles simulated
+system.cpu.num_insts                       1819780129                       # Number of instructions executed
+system.cpu.num_refs                         606571345                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr
new file mode 100644 (file)
index 0000000..87866a2
--- /dev/null
@@ -0,0 +1 @@
+warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout
new file mode 100644 (file)
index 0000000..0c5c001
--- /dev/null
@@ -0,0 +1,14 @@
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!