[binutils][aarch64] New sve_size_tsz_bhs iclass.

Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
	iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass decode.

diff --git a/include/ChangeLog b/include/ChangeLog
index f9650c805b4eb2d125098df6122e866f4d538413..8a990f35dc83d62bd95f6135842d56d2b5eaa72b 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
+       iclass.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 25201cf1899cffac2c443f09b4959d2c1dfe0d70..e354e65045f7a09a4c5fdda8d42d5e92d95dcd95 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -601,6 +601,7 @@ enum aarch64_insn_class
   sve_size_013,
   sve_shift_tsz_hsd,
   sve_shift_tsz_bhsd,
+  sve_size_tsz_bhs,
   testbranch,
   cryptosm3,
   cryptosm4,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b020582dd1222977f11795dacaa15945dff018b0..bb823cdde0ece6bb4137a712632451effa246079 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+       sve_size_tsz_bhs iclass encode.
+       * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+       sve_size_tsz_bhs iclass decode.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * aarch64-asm-2.c: Regenerated.

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index ad50598fd0e60154cbe5e7bd0ebb6472376c3a17..afb0e5b4d2ad0e62307e97858062f8599169248e 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1673,6 +1673,12 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
                    aarch64_get_variant (inst) + 1, 0);
       break;
 
+    case sve_size_tsz_bhs:
+      insert_fields (&inst->value,
+                    (1 << aarch64_get_variant (inst)),
+                    0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
+      break;
+
     case sve_size_013:
       variant = aarch64_get_variant (inst);
       if (variant == 2)

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index b42e4d594c6745143b6f37bff5337aa3632eae43..6b53a2c3228aea3117e0f45450dc9f192eedd6de 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2843,6 +2843,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
        }
       break;
 
+    case sve_size_tsz_bhs:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
+      while (i != 1)
+       {
+         if (i & 1)
+           return FALSE;
+         i >>= 1;
+         variant += 1;
+       }
+      break;
+
     case sve_shift_tsz_hsd:
       i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
       if (i == 0)