C_SOURCES = \
r600_buffer.c \
+ r600_state2.c \
r600_context.c \
r600_shader.c \
r600_draw.c \
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+#ifndef R600_H
+#define R600_H
+
+#include <stdint.h>
+#include <stdio.h>
+
+#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
+
+#define R600_ERR(fmt, args...) \
+ fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
+
+typedef uint64_t u64;
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+struct radeon;
+
+enum radeon_family {
+ CHIP_UNKNOWN,
+ CHIP_R100,
+ CHIP_RV100,
+ CHIP_RS100,
+ CHIP_RV200,
+ CHIP_RS200,
+ CHIP_R200,
+ CHIP_RV250,
+ CHIP_RS300,
+ CHIP_RV280,
+ CHIP_R300,
+ CHIP_R350,
+ CHIP_RV350,
+ CHIP_RV380,
+ CHIP_R420,
+ CHIP_R423,
+ CHIP_RV410,
+ CHIP_RS400,
+ CHIP_RS480,
+ CHIP_RS600,
+ CHIP_RS690,
+ CHIP_RS740,
+ CHIP_RV515,
+ CHIP_R520,
+ CHIP_RV530,
+ CHIP_RV560,
+ CHIP_RV570,
+ CHIP_R580,
+ CHIP_R600,
+ CHIP_RV610,
+ CHIP_RV630,
+ CHIP_RV670,
+ CHIP_RV620,
+ CHIP_RV635,
+ CHIP_RS780,
+ CHIP_RS880,
+ CHIP_RV770,
+ CHIP_RV730,
+ CHIP_RV710,
+ CHIP_RV740,
+ CHIP_CEDAR,
+ CHIP_REDWOOD,
+ CHIP_JUNIPER,
+ CHIP_CYPRESS,
+ CHIP_HEMLOCK,
+ CHIP_LAST,
+};
+
+enum radeon_family r600_get_family(struct radeon *rw);
+
+/*
+ * radeon object functions
+ */
+#if 0
+struct radeon_bo {
+ unsigned refcount;
+ unsigned handle;
+ unsigned size;
+ unsigned alignment;
+ unsigned map_count;
+ void *data;
+};
+struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
+ unsigned size, unsigned alignment, void *ptr);
+int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
+void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
+struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
+struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
+int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
+#endif
+/* lowlevel WS bo */
+struct radeon_ws_bo;
+struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
+ unsigned size, unsigned alignment, unsigned usage);
+struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
+ unsigned handle);
+void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
+void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
+void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
+ struct radeon_ws_bo *src);
+int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *bo);
+
+/* R600/R700 STATES */
+#define R600_GROUP_MAX 16
+#define R600_BLOCK_MAX_BO 32
+#define R600_BLOCK_MAX_REG 128
+
+enum r600_group_id {
+ R600_GROUP_CONFIG = 0,
+ R600_GROUP_CONTEXT,
+ R600_GROUP_ALU_CONST,
+ R600_GROUP_RESOURCE,
+ R600_GROUP_SAMPLER,
+ R600_GROUP_CTL_CONST,
+ R600_GROUP_LOOP_CONST,
+ R600_GROUP_BOOL_CONST,
+ R600_NGROUPS
+};
+
+struct r600_pipe_reg {
+ unsigned group_id;
+ u32 offset;
+ u32 mask;
+ u32 value;
+ struct radeon_ws_bo *bo;
+};
+
+struct r600_pipe_state {
+ unsigned id;
+ unsigned nregs;
+ struct r600_pipe_reg regs[R600_BLOCK_MAX_REG];
+};
+
+static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
+ unsigned group_id, u32 offset,
+ u32 value, u32 mask,
+ struct radeon_ws_bo *bo)
+{
+ state->regs[state->nregs].group_id = group_id;
+ state->regs[state->nregs].offset = offset;
+ state->regs[state->nregs].value = value;
+ state->regs[state->nregs].mask = mask;
+ state->regs[state->nregs].bo = bo;
+ state->nregs++;
+ assert(state->nregs < R600_BLOCK_MAX_REG);
+}
+
+#define R600_BLOCK_STATUS_ENABLED (1 << 0)
+#define R600_BLOCK_STATUS_DIRTY (1 << 1)
+
+struct r600_block_reloc {
+ struct radeon_ws_bo *bo;
+ unsigned nreloc;
+ unsigned bo_pm4_index[R600_BLOCK_MAX_BO];
+};
+
+struct r600_group_block {
+ unsigned status;
+ unsigned start_offset;
+ unsigned pm4_ndwords;
+ unsigned nbo;
+ unsigned nreg;
+ u32 pm4[R600_BLOCK_MAX_REG];
+ unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
+ struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
+};
+
+struct r600_group {
+ unsigned start_offset;
+ unsigned end_offset;
+ unsigned nblocks;
+ struct r600_group_block *blocks;
+ unsigned *offset_block_id;
+};
+
+#pragma pack(1)
+struct r600_reloc {
+ uint32_t handle;
+ uint32_t read_domain;
+ uint32_t write_domain;
+ uint32_t flags;
+};
+#pragma pack()
+
+struct r600_context {
+ struct radeon *radeon;
+ unsigned ngroups;
+ struct r600_group groups[R600_GROUP_MAX];
+ unsigned pm4_ndwords;
+ unsigned pm4_cdwords;
+ unsigned pm4_dirty_cdwords;
+ unsigned ctx_pm4_ndwords;
+ unsigned nreloc;
+ unsigned creloc;
+ struct r600_reloc *reloc;
+ struct radeon_ws_bo **bo;
+ u32 *pm4;
+};
+
+struct r600_draw {
+ u32 vgt_num_indices;
+ u32 vgt_num_instances;
+ u32 vgt_index_type;
+ u32 vgt_draw_initiator;
+ u32 indices_bo_offset;
+ struct radeon_ws_bo *indices;
+};
+
+int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
+void r600_context_fini(struct r600_context *ctx);
+void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+void r600_context_flush(struct r600_context *ctx);
+void r600_context_dump_bof(struct r600_context *ctx, const char *file);
+void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
+
+#endif
r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
}
-void r600_init_screen_resource_functions(struct r600_screen *r600screen)
+void r600_init_screen_resource_functions(struct pipe_screen *screen)
{
- r600screen->screen.resource_create = r600_resource_create;
- r600screen->screen.resource_from_handle = r600_resource_from_handle;
- r600screen->screen.resource_get_handle = u_resource_get_handle_vtbl;
- r600screen->screen.resource_destroy = u_resource_destroy_vtbl;
- r600screen->screen.user_buffer_create = r600_user_buffer_create;
+ screen->resource_create = r600_resource_create;
+ screen->resource_from_handle = r600_resource_from_handle;
+ screen->resource_get_handle = u_resource_get_handle_vtbl;
+ screen->resource_destroy = u_resource_destroy_vtbl;
+ screen->user_buffer_create = r600_user_buffer_create;
}
};
void r600_init_context_resource_functions(struct r600_context *r600);
-void r600_init_screen_resource_functions(struct r600_screen *r600screen);
+void r600_init_screen_resource_functions(struct pipe_screen *screen);
/* r600_buffer */
u32 r600_domain_from_usage(unsigned usage);
rscreen->screen.is_format_supported = r600_is_format_supported;
rscreen->screen.context_create = r600_create_context;
r600_init_screen_texture_functions(&rscreen->screen);
- r600_init_screen_resource_functions(rscreen);
+ r600_init_screen_resource_functions(&rscreen->screen);
return &rscreen->screen;
}
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* TODO:
+ * - fix mask for depth control & cull for query
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_blitter.h>
+#include <util/u_double_list.h>
+#include <util/u_transfer.h>
+#include <util/u_surface.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <pipebuffer/pb_buffer.h>
+#include "state_tracker/drm_driver.h"
+#include "r600.h"
+#include "r600d.h"
+#include "r700_sq.h"
+struct radeon_state {
+ unsigned dummy;
+};
+#include "r600_resource.h"
+#include "r600_shader.h"
+
+
+uint32_t r600_translate_texformat(enum pipe_format format,
+ const unsigned char *swizzle_view,
+ uint32_t *word4_p, uint32_t *yuv_format_p);
+
+#include "r600_state_inlines.h"
+
+enum chip_class {
+ R600,
+ R700,
+ EVERGREEN,
+};
+
+enum r600_pipe_state_id {
+ R600_PIPE_STATE_BLEND = 0,
+ R600_PIPE_STATE_BLEND_COLOR,
+ R600_PIPE_STATE_CONFIG,
+ R600_PIPE_STATE_CLIP,
+ R600_PIPE_STATE_SCISSOR,
+ R600_PIPE_STATE_VIEWPORT,
+ R600_PIPE_STATE_RASTERIZER,
+ R600_PIPE_STATE_VGT,
+ R600_PIPE_STATE_FRAMEBUFFER,
+ R600_PIPE_STATE_DSA,
+ R600_PIPE_STATE_STENCIL_REF,
+ R600_PIPE_STATE_PS_SHADER,
+ R600_PIPE_STATE_VS_SHADER,
+ R600_PIPE_STATE_CONSTANT,
+ R600_PIPE_STATE_SAMPLER,
+ R600_PIPE_STATE_RESOURCE,
+ R600_PIPE_NSTATES
+};
+
+struct r600_screen {
+ struct pipe_screen screen;
+ struct radeon *radeon;
+ unsigned chip_class;
+};
+
+struct r600_pipe_sampler_view {
+ struct pipe_sampler_view base;
+ struct r600_pipe_state state;
+};
+
+struct r600_pipe_rasterizer {
+ struct r600_pipe_state rstate;
+ bool flatshade;
+ unsigned sprite_coord_enable;
+};
+
+struct r600_pipe_blend {
+ struct r600_pipe_state rstate;
+ unsigned cb_target_mask;
+};
+
+struct r600_pipe_shader {
+ struct r600_shader shader;
+ struct r600_pipe_state rstate;
+ struct radeon_ws_bo *bo;
+};
+
+struct r600_vertex_element
+{
+ unsigned count;
+ unsigned refcount;
+ struct pipe_vertex_element elements[32];
+};
+
+struct r600_pipe_context {
+ struct pipe_context context;
+ struct r600_screen *screen;
+ struct radeon *radeon;
+ struct blitter_context *blitter;
+ struct r600_pipe_state *states[R600_PIPE_NSTATES];
+ struct r600_context ctx;
+ struct r600_vertex_element *vertex_elements;
+ struct pipe_framebuffer_state framebuffer;
+ struct pipe_index_buffer index_buffer;
+ struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+ unsigned nvertex_buffer;
+ unsigned cb_target_mask;
+ /* for saving when using blitter */
+ struct pipe_stencil_ref stencil_ref;
+ struct pipe_viewport_state viewport;
+ struct pipe_clip_state clip;
+ unsigned vs_nconst;
+ unsigned ps_nconst;
+ struct r600_pipe_state vs_const[256];
+ struct r600_pipe_state ps_const[256];
+ struct r600_pipe_state vs_resource[160];
+ struct r600_pipe_state ps_resource[160];
+ struct r600_pipe_state config;
+ struct r600_pipe_shader *ps_shader;
+ struct r600_pipe_shader *vs_shader;
+ /* shader information */
+ bool ps_rebuild;
+ bool vs_rebuild;
+ unsigned sprite_coord_enable;
+ bool flatshade;
+};
+
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+ return value * (1 << frac_bits);
+}
+
+/* r600_shader.c */
+static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_shader *rshader = &shader->shader;
+ unsigned spi_vs_out_id[10];
+ unsigned i, tmp;
+
+ /* clear previous register */
+ rstate->nregs = 0;
+
+ /* so far never got proper semantic id from tgsi */
+ for (i = 0; i < 10; i++) {
+ spi_vs_out_id[i] = 0;
+ }
+ for (i = 0; i < 32; i++) {
+ tmp = i << ((i & 3) * 8);
+ spi_vs_out_id[i / 4] |= tmp;
+ }
+ for (i = 0; i < 10; i++) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028614_SPI_VS_OUT_ID_0 + i * 4,
+ spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+ }
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0286C4_SPI_VS_OUT_CONFIG,
+ S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028868_SQ_PGM_RESOURCES_VS,
+ S_028868_NUM_GPRS(rshader->bc.ngpr) |
+ S_028868_STACK_SIZE(rshader->bc.nstack),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0288A4_SQ_PGM_RESOURCES_FS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0288D0_SQ_PGM_CF_OFFSET_VS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0288DC_SQ_PGM_CF_OFFSET_FS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028858_SQ_PGM_START_VS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028894_SQ_PGM_START_FS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ rctx->vs_rebuild = false;
+}
+
+static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = &shader->rstate;
+ struct r600_shader *rshader = &shader->shader;
+ unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
+ boolean have_pos = FALSE;
+
+ /* clear previous register */
+ rstate->nregs = 0;
+
+ for (i = 0; i < rshader->ninput; i++) {
+ tmp = S_028644_SEMANTIC(i);
+ tmp |= S_028644_SEL_CENTROID(1);
+ if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+ have_pos = TRUE;
+ if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+ rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+ rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+ tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+ }
+ if (rctx->sprite_coord_enable & (1 << i)) {
+ tmp |= S_028644_PT_SPRITE_TEX(1);
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
+ }
+
+ exports_ps = 0;
+ num_cout = 0;
+ for (i = 0; i < rshader->noutput; i++) {
+ if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+ exports_ps |= 1;
+ else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+ exports_ps |= (1 << (num_cout+1));
+ num_cout++;
+ }
+ }
+ if (!exports_ps) {
+ /* always at least export 1 component per pixel */
+ exports_ps = 2;
+ }
+
+ spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
+ S_0286CC_PERSP_GRADIENT_ENA(1);
+ spi_input_z = 0;
+ if (have_pos) {
+ spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
+ S_0286CC_BARYC_SAMPLE_CNTL(1);
+ spi_input_z |= 1;
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028840_SQ_PGM_START_PS,
+ 0x00000000, 0xFFFFFFFF, shader->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028850_SQ_PGM_RESOURCES_PS,
+ S_028868_NUM_GPRS(rshader->bc.ngpr) |
+ S_028868_STACK_SIZE(rshader->bc.nstack),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028854_SQ_PGM_EXPORTS_PS,
+ exports_ps, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0288CC_SQ_PGM_CF_OFFSET_PS,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ rctx->ps_rebuild = false;
+}
+
+static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_shader *rshader = &shader->shader;
+ void *ptr;
+
+ /* copy new shader */
+ if (shader->bo == NULL) {
+ shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
+ if (shader->bo == NULL) {
+ return -ENOMEM;
+ }
+ ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
+ memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
+ radeon_ws_bo_unmap(rctx->radeon, shader->bo);
+ }
+ /* build state */
+ rshader->flat_shade = rctx->flatshade;
+ switch (rshader->processor_type) {
+ case TGSI_PROCESSOR_VERTEX:
+ r600_pipe_shader_vs(ctx, shader);
+ break;
+ case TGSI_PROCESSOR_FRAGMENT:
+ r600_pipe_shader_ps(ctx, shader);
+ break;
+ default:
+ return -EINVAL;
+ }
+ r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
+ return 0;
+}
+
+static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_shader *shader = &rshader->shader;
+ const struct util_format_description *desc;
+ enum pipe_format resource_format[160];
+ unsigned i, nresources = 0;
+ struct r600_bc *bc = &shader->bc;
+ struct r600_bc_cf *cf;
+ struct r600_bc_vtx *vtx;
+
+ if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
+ return 0;
+ for (i = 0; i < rctx->vertex_elements->count; i++) {
+ resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
+ }
+ radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
+ LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
+ switch (cf->inst) {
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+ LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+ desc = util_format_description(resource_format[vtx->buffer_id]);
+ if (desc == NULL) {
+ R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
+ return -EINVAL;
+ }
+ vtx->dst_sel_x = desc->swizzle[0];
+ vtx->dst_sel_y = desc->swizzle[1];
+ vtx->dst_sel_z = desc->swizzle[2];
+ vtx->dst_sel_w = desc->swizzle[3];
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return r600_bc_build(&shader->bc);
+}
+
+static int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ int r;
+
+ if (shader == NULL)
+ return -EINVAL;
+ if (shader->bo) {
+ switch (shader->shader.processor_type) {
+ case TGSI_PROCESSOR_VERTEX:
+ if (!rctx->vs_rebuild)
+ return 0;
+ break;
+ case TGSI_PROCESSOR_FRAGMENT:
+ if (!rctx->ps_rebuild)
+ return 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+ /* there should be enough input */
+ if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
+ R600_ERR("%d resources provided, expecting %d\n",
+ rctx->vertex_elements->count, shader->shader.bc.nresource);
+ return -EINVAL;
+ }
+ r = r600_shader_update(ctx, shader);
+ if (r)
+ return r;
+ return r600_pipe_shader(ctx, shader);
+}
+
+int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
+static int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ int r;
+
+//fprintf(stderr, "--------------------------------------------------------------\n");
+//tgsi_dump(tokens, 0);
+ shader->shader.family = r600_get_family(rctx->radeon);
+ r = r600_shader_from_tgsi(tokens, &shader->shader);
+ if (r) {
+ R600_ERR("translation from TGSI failed !\n");
+ return r;
+ }
+ r = r600_bc_build(&shader->shader.bc);
+ if (r) {
+ R600_ERR("building bytecode failed !\n");
+ return r;
+ }
+//fprintf(stderr, "______________________________________________________________\n");
+ return 0;
+}
+/* r600_shader.c END */
+
+static const char* r600_get_vendor(struct pipe_screen* pscreen)
+{
+ return "X.Org";
+}
+
+static const char* r600_get_name(struct pipe_screen* pscreen)
+{
+ struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+ enum radeon_family family = r600_get_family(rscreen->radeon);
+
+ if (family >= CHIP_R600 && family < CHIP_RV770)
+ return "R600 (HD2XXX,HD3XXX)";
+ else
+ return "R700 (HD4XXX)";
+}
+
+static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+ switch (param) {
+ /* Supported features (boolean caps). */
+ case PIPE_CAP_NPOT_TEXTURES:
+ case PIPE_CAP_TWO_SIDED_STENCIL:
+ case PIPE_CAP_GLSL:
+ case PIPE_CAP_DUAL_SOURCE_BLEND:
+ case PIPE_CAP_ANISOTROPIC_FILTER:
+ case PIPE_CAP_POINT_SPRITE:
+ case PIPE_CAP_OCCLUSION_QUERY:
+ case PIPE_CAP_TEXTURE_SHADOW_MAP:
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
+ case PIPE_CAP_BLEND_EQUATION_SEPARATE:
+ case PIPE_CAP_SM3:
+ case PIPE_CAP_TEXTURE_SWIZZLE:
+ case PIPE_CAP_INDEP_BLEND_ENABLE:
+ case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
+ case PIPE_CAP_DEPTH_CLAMP:
+ return 1;
+
+ /* Unsupported features (boolean caps). */
+ case PIPE_CAP_TIMER_QUERY:
+ case PIPE_CAP_STREAM_OUTPUT:
+ case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
+ return 0;
+
+ /* Texturing. */
+ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+ return 14;
+ case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
+ /* FIXME allow this once infrastructure is there */
+ return 0;
+ case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
+ case PIPE_CAP_MAX_COMBINED_SAMPLERS:
+ return 16;
+
+ /* Render targets. */
+ case PIPE_CAP_MAX_RENDER_TARGETS:
+ /* FIXME some r6xx are buggy and can only do 4 */
+ return 8;
+
+ /* Fragment coordinate conventions. */
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+ return 1;
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+ return 0;
+
+ default:
+ R600_ERR("r600: unknown param %d\n", param);
+ return 0;
+ }
+}
+
+static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+ switch (param) {
+ case PIPE_CAP_MAX_LINE_WIDTH:
+ case PIPE_CAP_MAX_LINE_WIDTH_AA:
+ case PIPE_CAP_MAX_POINT_WIDTH:
+ case PIPE_CAP_MAX_POINT_WIDTH_AA:
+ return 8192.0f;
+ case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+ return 16.0f;
+ case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+ return 16.0f;
+ default:
+ R600_ERR("r600: unsupported paramf %d\n", param);
+ return 0.0f;
+ }
+}
+
+static boolean r600_is_format_supported(struct pipe_screen* screen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned sample_count,
+ unsigned usage,
+ unsigned geom_flags)
+{
+ unsigned retval = 0;
+ if (target >= PIPE_MAX_TEXTURE_TYPES) {
+ R600_ERR("r600: unsupported texture type %d\n", target);
+ return FALSE;
+ }
+
+ /* Multisample */
+ if (sample_count > 1)
+ return FALSE;
+
+ if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+ r600_is_sampler_format_supported(format)) {
+ retval |= PIPE_BIND_SAMPLER_VIEW;
+ }
+
+ if ((usage & (PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED)) &&
+ r600_is_colorbuffer_format_supported(format)) {
+ retval |= usage &
+ (PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED);
+ }
+
+ if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+ r600_is_zs_format_supported(format)) {
+ retval |= PIPE_BIND_DEPTH_STENCIL;
+ }
+
+ if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+ r600_is_vertex_format_supported(format))
+ retval |= PIPE_BIND_VERTEX_BUFFER;
+
+ if (usage & PIPE_BIND_TRANSFER_READ)
+ retval |= PIPE_BIND_TRANSFER_READ;
+ if (usage & PIPE_BIND_TRANSFER_WRITE)
+ retval |= PIPE_BIND_TRANSFER_WRITE;
+
+ return retval == usage;
+}
+
+static void r600_destroy_screen(struct pipe_screen* pscreen)
+{
+ struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+
+ if (rscreen == NULL)
+ return;
+ FREE(rscreen);
+}
+
+struct r600_drawl {
+ struct pipe_context *ctx;
+ unsigned mode;
+ unsigned start;
+ unsigned count;
+ unsigned index_size;
+ struct pipe_resource *index_buffer;
+};
+
+int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
+static void r600_draw_common(struct r600_drawl *draw)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
+ struct r600_pipe_state *rstate;
+ struct r600_resource *rbuffer;
+ unsigned i, j, offset, format, prim;
+ u32 vgt_dma_index_type, vgt_draw_initiator, mask;
+ struct pipe_vertex_buffer *vertex_buffer;
+ struct r600_draw rdraw;
+ struct r600_pipe_state vgt;
+
+ switch (draw->index_size) {
+ case 2:
+ vgt_draw_initiator = 0;
+ vgt_dma_index_type = 0;
+ break;
+ case 4:
+ vgt_draw_initiator = 0;
+ vgt_dma_index_type = 1;
+ break;
+ case 0:
+ vgt_draw_initiator = 2;
+ vgt_dma_index_type = 0;
+ break;
+ default:
+ R600_ERR("unsupported index size %d\n", draw->index_size);
+ return;
+ }
+ if (r600_conv_pipe_prim(draw->mode, &prim))
+ return;
+
+ /* rebuild vertex shader if input format changed */
+ if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
+ return;
+ if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
+ return;
+
+ for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+ rstate = &rctx->vs_resource[i];
+ j = rctx->vertex_elements->elements[i].vertex_buffer_index;
+ vertex_buffer = &rctx->vertex_buffer[j];
+ rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+ offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
+ format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
+ rstate->id = R600_PIPE_STATE_RESOURCE;
+ rstate->nregs = 0;
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE,
+ R_038008_RESOURCE0_WORD2,
+ S_038008_STRIDE(vertex_buffer->stride) |
+ S_038008_DATA_FORMAT(format),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
+ r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
+ }
+
+ mask = 0;
+ for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+ mask |= (0xF << (i * 4));
+ }
+
+ vgt.id = R600_PIPE_STATE_VGT;
+ vgt.nregs = 0;
+ r600_pipe_state_add_reg(&vgt, R600_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw->start, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+ r600_context_pipe_state_set(&rctx->ctx, &vgt);
+
+ rdraw.vgt_num_indices = draw->count;
+ rdraw.vgt_num_instances = 1;
+ rdraw.vgt_index_type = vgt_dma_index_type;
+ rdraw.vgt_draw_initiator = vgt_draw_initiator;
+ rdraw.indices = NULL;
+ if (draw->index_buffer) {
+ rbuffer = (struct r600_resource*)draw->index_buffer;
+ rdraw.indices = rbuffer->bo;
+ }
+ r600_context_draw(&rctx->ctx, &rdraw);
+}
+
+static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_drawl draw;
+
+ assert(info->index_bias == 0);
+
+ draw.ctx = ctx;
+ draw.mode = info->mode;
+ draw.start = info->start;
+ draw.count = info->count;
+ if (info->indexed && rctx->index_buffer.buffer) {
+ draw.index_size = rctx->index_buffer.index_size;
+ draw.index_buffer = rctx->index_buffer.buffer;
+ assert(rctx->index_buffer.offset %
+ rctx->index_buffer.index_size == 0);
+ draw.start += rctx->index_buffer.offset /
+ rctx->index_buffer.index_size;
+ } else {
+ draw.index_size = 0;
+ draw.index_buffer = NULL;
+ }
+ r600_draw_common(&draw);
+}
+
+static void r600_flush2(struct pipe_context *ctx, unsigned flags,
+ struct pipe_fence_handle **fence)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ static int dc = 0;
+ char dname[256];
+
+ if (!rctx->ctx.pm4_cdwords)
+ return;
+
+#if 0
+ sprintf(dname, "gallium-%08d.bof", dc);
+ if (dc < 2) {
+ r600_context_dump_bof(&rctx->ctx, dname);
+ R600_ERR("dumped %s\n", dname);
+ }
+ dc++;
+#endif
+ r600_context_flush(&rctx->ctx);
+}
+
+static void r600_destroy_context(struct pipe_context *context)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
+
+ r600_context_fini(&rctx->ctx);
+ for (int i = 0; i < R600_PIPE_NSTATES; i++) {
+ free(rctx->states[i]);
+ }
+ FREE(rctx);
+}
+
+static void r600_blitter_save_states(struct pipe_context *ctx)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
+ util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
+ if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
+ util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
+ }
+ util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
+ util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
+ util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
+ util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
+ if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
+ util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
+ }
+ if (rctx->states[R600_PIPE_STATE_CLIP]) {
+ util_blitter_save_clip(rctx->blitter, &rctx->clip);
+ }
+ util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
+
+ rctx->vertex_elements = NULL;
+
+ /* TODO queries */
+}
+
+static void r600_clear(struct pipe_context *ctx, unsigned buffers,
+ const float *rgba, double depth, unsigned stencil)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+
+ r600_blitter_save_states(ctx);
+ util_blitter_clear(rctx->blitter, fb->width, fb->height,
+ fb->nr_cbufs, buffers, rgba, depth,
+ stencil);
+}
+
+static void r600_clear_render_target(struct pipe_context *ctx,
+ struct pipe_surface *dst,
+ const float *rgba,
+ unsigned dstx, unsigned dsty,
+ unsigned width, unsigned height)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+
+ util_blitter_save_framebuffer(rctx->blitter, fb);
+ util_blitter_clear_render_target(rctx->blitter, dst, rgba,
+ dstx, dsty, width, height);
+}
+
+static void r600_clear_depth_stencil(struct pipe_context *ctx,
+ struct pipe_surface *dst,
+ unsigned clear_flags,
+ double depth,
+ unsigned stencil,
+ unsigned dstx, unsigned dsty,
+ unsigned width, unsigned height)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+
+ util_blitter_save_framebuffer(rctx->blitter, fb);
+ util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
+ dstx, dsty, width, height);
+}
+
+
+static void r600_resource_copy_region(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ struct pipe_subresource subdst,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ struct pipe_subresource subsrc,
+ unsigned srcx, unsigned srcy, unsigned srcz,
+ unsigned width, unsigned height)
+{
+ util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
+ src, subsrc, srcx, srcy, srcz, width, height);
+}
+
+static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
+{
+ rctx->context.clear = r600_clear;
+ rctx->context.clear_render_target = r600_clear_render_target;
+ rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
+ rctx->context.resource_copy_region = r600_resource_copy_region;
+}
+
+static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
+{
+ r600->context.get_transfer = u_get_transfer_vtbl;
+ r600->context.transfer_map = u_transfer_map_vtbl;
+ r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
+ r600->context.transfer_unmap = u_transfer_unmap_vtbl;
+ r600->context.transfer_destroy = u_transfer_destroy_vtbl;
+ r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
+ r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
+}
+
+static void r600_set_blend_color(struct pipe_context *ctx,
+ const struct pipe_blend_color *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rstate->id = R600_PIPE_STATE_BLEND_COLOR;
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
+ free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
+ rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *r600_create_blend_state(struct pipe_context *ctx,
+ const struct pipe_blend_state *state)
+{
+ struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
+ struct r600_pipe_state *rstate;
+ u32 color_control, target_mask;
+
+ if (blend == NULL) {
+ return NULL;
+ }
+ rstate = &blend->rstate;
+
+ rstate->id = R600_PIPE_STATE_BLEND;
+
+ target_mask = 0;
+ color_control = S_028808_PER_MRT_BLEND(1);
+ if (state->logicop_enable) {
+ color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
+ } else {
+ color_control |= (0xcc << 16);
+ }
+ /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
+ if (state->independent_blend_enable) {
+ for (int i = 0; i < 8; i++) {
+ if (state->rt[i].blend_enable) {
+ color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+ }
+ target_mask |= (state->rt[i].colormask << (4 * i));
+ }
+ } else {
+ for (int i = 0; i < 8; i++) {
+ if (state->rt[0].blend_enable) {
+ color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+ }
+ target_mask |= (state->rt[0].colormask << (4 * i));
+ }
+ }
+ blend->cb_target_mask = target_mask;
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
+ color_control, 0xFFFFFFFF, NULL);
+
+ for (int i = 0; i < 8; i++) {
+ unsigned eqRGB = state->rt[i].rgb_func;
+ unsigned srcRGB = state->rt[i].rgb_src_factor;
+ unsigned dstRGB = state->rt[i].rgb_dst_factor;
+
+ unsigned eqA = state->rt[i].alpha_func;
+ unsigned srcA = state->rt[i].alpha_src_factor;
+ unsigned dstA = state->rt[i].alpha_dst_factor;
+ uint32_t bc = 0;
+
+ if (!state->rt[i].blend_enable)
+ continue;
+
+ bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+ bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+ bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+ if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+ bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
+ bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+ bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+ bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+ }
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
+ if (i == 0) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
+ }
+ }
+ return rstate;
+}
+
+static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
+ struct r600_pipe_state *rstate;
+
+ if (state == NULL)
+ return;
+ rstate = &blend->rstate;
+ rctx->states[rstate->id] = rstate;
+ rctx->cb_target_mask = blend->cb_target_mask;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *r600_create_dsa_state(struct pipe_context *ctx,
+ const struct pipe_depth_stencil_alpha_state *state)
+{
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+ unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+
+ if (rstate == NULL) {
+ return NULL;
+ }
+
+ rstate->id = R600_PIPE_STATE_DSA;
+ /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
+ /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
+ * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
+ * be set if shader use texkill instruction
+ */
+ db_shader_control = 0x210;
+ stencil_ref_mask = 0;
+ stencil_ref_mask_bf = 0;
+ db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+ S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+ S_028800_ZFUNC(state->depth.func);
+
+ /* stencil */
+ if (state->stencil[0].enabled) {
+ db_depth_control |= S_028800_STENCIL_ENABLE(1);
+ db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+ db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+ db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+ db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+
+ stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+ S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+ if (state->stencil[1].enabled) {
+ db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+ db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+ db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+ db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+ db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+ stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+ S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+ }
+ }
+
+ /* alpha */
+ alpha_test_control = 0;
+ alpha_ref = 0;
+ if (state->alpha.enabled) {
+ alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+ alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+ alpha_ref = fui(state->alpha.ref_value);
+ }
+
+ /* misc */
+ db_render_control = 0;
+ db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
+ S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
+ S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+ /* TODO db_render_override depends on query */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028430_DB_STENCILREFMASK, stencil_ref_mask,
+ 0xFFFFFFFF & C_028430_STENCILREF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
+ 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
+
+ return rstate;
+}
+
+static void *r600_create_rs_state(struct pipe_context *ctx,
+ const struct pipe_rasterizer_state *state)
+{
+ struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
+ struct r600_pipe_state *rstate;
+ float offset_units = 0, offset_scale = 0;
+ unsigned offset_db_fmt_cntl = 0;
+ unsigned tmp;
+ unsigned prov_vtx = 1;
+
+ if (rs == NULL) {
+ return NULL;
+ }
+
+ rstate = &rs->rstate;
+ rs->flatshade = state->flatshade;
+ rs->sprite_coord_enable = state->sprite_coord_enable;
+
+ rstate->id = R600_PIPE_STATE_RASTERIZER;
+ if (state->flatshade_first)
+ prov_vtx = 0;
+ tmp = 0x00000001;
+ if (state->sprite_coord_enable) {
+ tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
+ S_0286D4_PNT_SPRITE_OVRD_X(2) |
+ S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+ S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+ S_0286D4_PNT_SPRITE_OVRD_W(1);
+ if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+ tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
+ }
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
+ S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+ S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+ S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+ S_028814_FACE(!state->front_ccw) |
+ S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+ S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+ S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
+ S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+ S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ /* point size 12.4 fixed point */
+ tmp = (unsigned)(state->point_size * 8.0);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+ return rstate;
+}
+
+static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ if (state == NULL)
+ return;
+
+ if (rctx->flatshade != rs->flatshade) {
+ rctx->ps_rebuild = true;
+ }
+ if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
+ rctx->ps_rebuild = true;
+ }
+ rctx->flatshade = rs->flatshade;
+ rctx->sprite_coord_enable = rs->sprite_coord_enable;
+
+ rctx->states[rs->rstate.id] = &rs->rstate;
+ r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
+}
+
+static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+
+ if (rctx->states[rs->rstate.id] == &rs->rstate) {
+ rctx->states[rs->rstate.id] = NULL;
+ }
+ free(rs);
+}
+
+static void *r600_create_sampler_state(struct pipe_context *ctx,
+ const struct pipe_sampler_state *state)
+{
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ union util_color uc;
+
+ if (rstate == NULL) {
+ return NULL;
+ }
+
+ rstate->id = R600_PIPE_STATE_SAMPLER;
+ util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
+ S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+ S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+ S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+ S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+ S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+ S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+ S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+ S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
+ /* FIXME LOD it depends on texture base level ... */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
+ S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+ S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
+ S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
+ if (uc.ui) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
+ }
+ return rstate;
+}
+
+static void *r600_create_vertex_elements(struct pipe_context *ctx,
+ unsigned count,
+ const struct pipe_vertex_element *elements)
+{
+ struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
+
+ assert(count < 32);
+ v->count = count;
+ v->refcount = 1;
+ memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
+ return v;
+}
+
+static void r600_sampler_view_destroy(struct pipe_context *ctx,
+ struct pipe_sampler_view *state)
+{
+ struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+
+ pipe_resource_reference(&state->texture, NULL);
+ FREE(resource);
+}
+
+static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *state)
+{
+ struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
+ struct r600_pipe_state *rstate;
+ const struct util_format_description *desc;
+ struct r600_resource_texture *tmp;
+ struct r600_resource *rbuffer;
+ unsigned format;
+ uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+ unsigned char swizzle[4], array_mode = 0, tile_type = 0;
+ struct radeon_ws_bo *bo[2];
+
+ if (resource == NULL)
+ return NULL;
+ rstate = &resource->state;
+
+ /* initialize base object */
+ resource->base = *state;
+ resource->base.texture = NULL;
+ pipe_reference(NULL, &texture->reference);
+ resource->base.texture = texture;
+ resource->base.reference.count = 1;
+ resource->base.context = ctx;
+
+ swizzle[0] = state->swizzle_r;
+ swizzle[1] = state->swizzle_g;
+ swizzle[2] = state->swizzle_b;
+ swizzle[3] = state->swizzle_a;
+ format = r600_translate_texformat(texture->format,
+ swizzle,
+ &word4, &yuv_format);
+ if (format == ~0) {
+ format = 0;
+ }
+ desc = util_format_description(texture->format);
+ if (desc == NULL) {
+ R600_ERR("unknow format %d\n", texture->format);
+ }
+ tmp = (struct r600_resource_texture*)texture;
+ rbuffer = &tmp->resource;
+ bo[0] = rbuffer->bo;
+ bo[1] = rbuffer->bo;
+ /* FIXME depth texture decompression */
+ if (tmp->depth) {
+#if 0
+ r = r600_texture_from_depth(ctx, tmp, view->first_level);
+ if (r) {
+ return;
+ }
+ bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
+ bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
+#endif
+ }
+ pitch = (tmp->pitch[0] / tmp->bpt);
+ pitch = (pitch + 0x7) & ~0x7;
+
+ /* FIXME properly handle first level != 0 */
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0,
+ S_038000_DIM(r600_tex_dim(texture->target)) |
+ S_038000_TILE_MODE(array_mode) |
+ S_038000_TILE_TYPE(tile_type) |
+ S_038000_PITCH((pitch / 8) - 1) |
+ S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1,
+ S_038004_TEX_HEIGHT(texture->height0 - 1) |
+ S_038004_TEX_DEPTH(texture->depth0 - 1) |
+ S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038008_RESOURCE0_WORD2,
+ tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3,
+ tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4,
+ word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
+ S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
+ S_038010_REQUEST_SIZE(1) |
+ S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5,
+ S_038014_LAST_LEVEL(state->last_level) |
+ S_038014_BASE_ARRAY(0) |
+ S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6,
+ S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+
+ return &resource->base;
+}
+
+static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ /* TODO */
+ assert(1);
+}
+
+static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
+
+ for (int i = 0; i < count; i++) {
+ if (resource[i]) {
+ r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
+ }
+ }
+}
+
+static void r600_bind_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+ if (state == NULL)
+ return;
+ rctx->states[rstate->id] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+ for (int i = 0; i < count; i++) {
+ r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
+ }
+}
+
+static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+ /* TODO implement */
+ for (int i = 0; i < count; i++) {
+ r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
+ }
+}
+
+static void r600_delete_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+ if (rctx->states[rstate->id] == rstate) {
+ rctx->states[rstate->id] = NULL;
+ }
+ for (int i = 0; i < rstate->nregs; i++) {
+ radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+ }
+ free(rstate);
+}
+
+static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+ struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+ if (v == NULL)
+ return;
+ if (--v->refcount)
+ return;
+ free(v);
+}
+
+static void r600_set_clip_state(struct pipe_context *ctx,
+ const struct pipe_clip_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rctx->clip = *state;
+ rstate->id = R600_PIPE_STATE_CLIP;
+ for (int i = 0; i < state->nr; i++) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028E20_PA_CL_UCP0_X + i * 4,
+ fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028E24_PA_CL_UCP0_Y + i * 4,
+ fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028E28_PA_CL_UCP0_Z + i * 4,
+ fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028E2C_PA_CL_UCP0_W + i * 4,
+ fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
+ S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
+ S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
+ S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_CLIP]);
+ rctx->states[R600_PIPE_STATE_CLIP] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+ r600_delete_vertex_element(ctx, rctx->vertex_elements);
+ rctx->vertex_elements = v;
+ if (v) {
+ v->refcount++;
+ rctx->vs_rebuild = true;
+ }
+}
+
+static void r600_set_polygon_stipple(struct pipe_context *ctx,
+ const struct pipe_poly_stipple *state)
+{
+}
+
+static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void r600_set_scissor_state(struct pipe_context *ctx,
+ const struct pipe_scissor_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ u32 tl, br;
+
+ if (rstate == NULL)
+ return;
+
+ rstate->id = R600_PIPE_STATE_SCISSOR;
+ tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
+ br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028210_PA_SC_CLIPRECT_0_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028214_PA_SC_CLIPRECT_0_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028218_PA_SC_CLIPRECT_1_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02821C_PA_SC_CLIPRECT_1_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028220_PA_SC_CLIPRECT_2_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028224_PA_SC_CLIPRECT_2_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028228_PA_SC_CLIPRECT_3_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02822C_PA_SC_CLIPRECT_3_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
+ 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_SCISSOR]);
+ rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_set_stencil_ref(struct pipe_context *ctx,
+ const struct pipe_stencil_ref *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ u32 tmp;
+
+ if (rstate == NULL)
+ return;
+
+ rctx->stencil_ref = *state;
+ rstate->id = R600_PIPE_STATE_STENCIL_REF;
+ tmp = S_028430_STENCILREF(state->ref_value[0]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028430_DB_STENCILREFMASK, tmp,
+ ~C_028430_STENCILREF, NULL);
+ tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028434_DB_STENCILREFMASK_BF, tmp,
+ ~C_028434_STENCILREF_BF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
+ rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_set_viewport_state(struct pipe_context *ctx,
+ const struct pipe_viewport_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rctx->viewport = *state;
+ rstate->id = R600_PIPE_STATE_VIEWPORT;
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
+ rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+ const struct pipe_framebuffer_state *state, int cb)
+{
+ struct r600_resource_texture *rtex;
+ struct r600_resource *rbuffer;
+ unsigned level = state->cbufs[cb]->level;
+ unsigned pitch, slice;
+ unsigned color_info;
+ unsigned format, swap, ntype;
+ const struct util_format_description *desc;
+ struct radeon_ws_bo *bo[3];
+
+ rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+ rbuffer = &rtex->resource;
+ bo[0] = rbuffer->bo;
+ bo[1] = rbuffer->bo;
+ bo[2] = rbuffer->bo;
+
+ pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+ slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+ ntype = 0;
+ desc = util_format_description(rtex->resource.base.b.format);
+ if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+ ntype = V_0280A0_NUMBER_SRGB;
+
+ format = r600_translate_colorformat(rtex->resource.base.b.format);
+ swap = r600_translate_colorswap(rtex->resource.base.b.format);
+ color_info = S_0280A0_FORMAT(format) |
+ S_0280A0_COMP_SWAP(swap) |
+ S_0280A0_BLEND_CLAMP(1) |
+ S_0280A0_SOURCE_FORMAT(1) |
+ S_0280A0_NUMBER_TYPE(ntype);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028040_CB_COLOR0_BASE + cb * 4,
+ state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0280A0_CB_COLOR0_INFO + cb * 4,
+ color_info, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028060_CB_COLOR0_SIZE + cb * 4,
+ S_028060_PITCH_TILE_MAX(pitch) |
+ S_028060_SLICE_TILE_MAX(slice),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028080_CB_COLOR0_VIEW + cb * 4,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0280E0_CB_COLOR0_FRAG + cb * 4,
+ 0x00000000, 0xFFFFFFFF, bo[1]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_0280C0_CB_COLOR0_TILE + cb * 4,
+ 0x00000000, 0xFFFFFFFF, bo[2]);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028100_CB_COLOR0_MASK + cb * 4,
+ 0x00000000, 0xFFFFFFFF, NULL);
+}
+
+static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+ const struct pipe_framebuffer_state *state)
+{
+ struct r600_resource_texture *rtex;
+ struct r600_resource *rbuffer;
+ unsigned level;
+ unsigned pitch, slice, format;
+
+ if (state->zsbuf == NULL)
+ return;
+
+ rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+ rtex->tilled = 1;
+ rtex->array_mode = 2;
+ rtex->tile_type = 1;
+ rtex->depth = 1;
+ rbuffer = &rtex->resource;
+
+ level = state->zsbuf->level;
+ pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+ slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+ format = r600_translate_dbformat(state->zsbuf->texture->format);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02800C_DB_DEPTH_BASE,
+ state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028000_DB_DEPTH_SIZE,
+ S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028010_DB_DEPTH_INFO,
+ S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D34_DB_PREFETCH_LIMIT,
+ (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
+}
+
+static void r600_set_framebuffer_state(struct pipe_context *ctx,
+ const struct pipe_framebuffer_state *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ u32 shader_mask, tl, br, shader_control, target_mask;
+
+ if (rstate == NULL)
+ return;
+
+ /* unreference old buffer and reference new one */
+ rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
+ for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+ pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
+ }
+ pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
+ rctx->framebuffer = *state;
+
+ /* build states */
+ for (int i = 0; i < state->nr_cbufs; i++) {
+ r600_cb(rctx, rstate, state, i);
+ }
+ if (state->zsbuf) {
+ r600_db(rctx, rstate, state);
+ }
+
+ target_mask = 0x00000000;
+ target_mask = 0xFFFFFFFF;
+ shader_mask = 0;
+ shader_control = 0;
+ for (int i = 0; i < state->nr_cbufs; i++) {
+ target_mask ^= 0xf << (i * 4);
+ shader_mask |= 0xf << (i * 4);
+ shader_control |= 1 << i;
+ }
+ tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
+ br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
+ 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
+ R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
+ 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0287A0_CB_SHADER_CONTROL,
+ shader_control, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
+ 0x00000000, target_mask, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
+ shader_mask, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C30_CB_CLRCMP_CONTROL,
+ 0x01000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C34_CB_CLRCMP_SRC,
+ 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C38_CB_CLRCMP_DST,
+ 0x000000FF, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C3C_CB_CLRCMP_MSK,
+ 0xFFFFFFFF, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C48_PA_SC_AA_MASK,
+ 0xFFFFFFFF, 0xFFFFFFFF, NULL);
+
+ free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
+ rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_set_index_buffer(struct pipe_context *ctx,
+ const struct pipe_index_buffer *ib)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ if (ib) {
+ pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+ memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
+ } else {
+ pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+ memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
+ }
+
+ /* TODO make this more like a state */
+}
+
+static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+ const struct pipe_vertex_buffer *buffers)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ for (int i = 0; i < rctx->nvertex_buffer; i++) {
+ pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+ }
+ memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+ for (int i = 0; i < count; i++) {
+ rctx->vertex_buffer[i].buffer = NULL;
+ pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+ }
+ rctx->nvertex_buffer = count;
+}
+
+static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+ struct pipe_resource *buffer)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_state *rstate;
+ struct pipe_transfer *transfer;
+ unsigned *nconst = NULL;
+ u32 *ptr, offset;
+
+ switch (shader) {
+ case PIPE_SHADER_VERTEX:
+ rstate = rctx->vs_const;
+ nconst = &rctx->vs_nconst;
+ offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
+ break;
+ case PIPE_SHADER_FRAGMENT:
+ rstate = rctx->ps_const;
+ nconst = &rctx->ps_nconst;
+ offset = R_030000_SQ_ALU_CONSTANT0_0;
+ break;
+ default:
+ R600_ERR("unsupported %d\n", shader);
+ return;
+ }
+ if (buffer && buffer->width0 > 0) {
+ *nconst = buffer->width0 / 16;
+ ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
+ if (ptr == NULL)
+ return;
+ for (int i = 0; i < *nconst; i++, offset += 0x10) {
+ rstate[i].nregs = 0;
+ r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
+ r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
+ }
+ pipe_buffer_unmap(ctx, buffer, transfer);
+ }
+}
+
+static void *r600_create_shader_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
+ int r;
+
+ r = r600_pipe_shader_create2(ctx, shader, state->tokens);
+ if (r) {
+ return NULL;
+ }
+ return shader;
+}
+
+static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ /* TODO delete old shader */
+ rctx->ps_shader = (struct r600_pipe_shader *)state;
+}
+
+static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ /* TODO delete old shader */
+ rctx->vs_shader = (struct r600_pipe_shader *)state;
+}
+
+static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+ if (rctx->ps_shader == shader) {
+ rctx->ps_shader = NULL;
+ }
+ /* TODO proper delete */
+ free(shader);
+}
+
+static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+ if (rctx->vs_shader == shader) {
+ rctx->vs_shader = NULL;
+ }
+ /* TODO proper delete */
+ free(shader);
+}
+
+static void r600_init_state_functions2(struct r600_pipe_context *rctx)
+{
+ rctx->context.create_blend_state = r600_create_blend_state;
+ rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
+ rctx->context.create_fs_state = r600_create_shader_state;
+ rctx->context.create_rasterizer_state = r600_create_rs_state;
+ rctx->context.create_sampler_state = r600_create_sampler_state;
+ rctx->context.create_sampler_view = r600_create_sampler_view;
+ rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
+ rctx->context.create_vs_state = r600_create_shader_state;
+ rctx->context.bind_blend_state = r600_bind_blend_state;
+ rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
+ rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
+ rctx->context.bind_fs_state = r600_bind_ps_shader;
+ rctx->context.bind_rasterizer_state = r600_bind_rs_state;
+ rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
+ rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
+ rctx->context.bind_vs_state = r600_bind_vs_shader;
+ rctx->context.delete_blend_state = r600_delete_state;
+ rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
+ rctx->context.delete_fs_state = r600_delete_ps_shader;
+ rctx->context.delete_rasterizer_state = r600_delete_rs_state;
+ rctx->context.delete_sampler_state = r600_delete_state;
+ rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
+ rctx->context.delete_vs_state = r600_delete_vs_shader;
+ rctx->context.set_blend_color = r600_set_blend_color;
+ rctx->context.set_clip_state = r600_set_clip_state;
+ rctx->context.set_constant_buffer = r600_set_constant_buffer;
+ rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
+ rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
+ rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
+ rctx->context.set_sample_mask = r600_set_sample_mask;
+ rctx->context.set_scissor_state = r600_set_scissor_state;
+ rctx->context.set_stencil_ref = r600_set_stencil_ref;
+ rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
+ rctx->context.set_index_buffer = r600_set_index_buffer;
+ rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
+ rctx->context.set_viewport_state = r600_set_viewport_state;
+ rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
+}
+
+static void r600_init_config2(struct r600_pipe_context *rctx)
+{
+ int ps_prio;
+ int vs_prio;
+ int gs_prio;
+ int es_prio;
+ int num_ps_gprs;
+ int num_vs_gprs;
+ int num_gs_gprs;
+ int num_es_gprs;
+ int num_temp_gprs;
+ int num_ps_threads;
+ int num_vs_threads;
+ int num_gs_threads;
+ int num_es_threads;
+ int num_ps_stack_entries;
+ int num_vs_stack_entries;
+ int num_gs_stack_entries;
+ int num_es_stack_entries;
+ enum radeon_family family;
+ struct r600_pipe_state *rstate = &rctx->config;
+ u32 tmp;
+
+ family = r600_get_family(rctx->radeon);
+ ps_prio = 0;
+ vs_prio = 1;
+ gs_prio = 2;
+ es_prio = 3;
+ switch (family) {
+ case CHIP_R600:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV630:
+ case CHIP_RV635:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 144;
+ num_vs_threads = 40;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV610:
+ case CHIP_RV620:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ default:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV670:
+ num_ps_gprs = 144;
+ num_vs_gprs = 40;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 136;
+ num_vs_threads = 48;
+ num_gs_threads = 4;
+ num_es_threads = 4;
+ num_ps_stack_entries = 40;
+ num_vs_stack_entries = 40;
+ num_gs_stack_entries = 32;
+ num_es_stack_entries = 16;
+ break;
+ case CHIP_RV770:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 188;
+ num_vs_threads = 60;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 256;
+ num_vs_stack_entries = 256;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV730:
+ case CHIP_RV740:
+ num_ps_gprs = 84;
+ num_vs_gprs = 36;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 188;
+ num_vs_threads = 60;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ case CHIP_RV710:
+ num_ps_gprs = 192;
+ num_vs_gprs = 56;
+ num_temp_gprs = 4;
+ num_gs_gprs = 0;
+ num_es_gprs = 0;
+ num_ps_threads = 144;
+ num_vs_threads = 48;
+ num_gs_threads = 0;
+ num_es_threads = 0;
+ num_ps_stack_entries = 128;
+ num_vs_stack_entries = 128;
+ num_gs_stack_entries = 0;
+ num_es_stack_entries = 0;
+ break;
+ }
+
+ rstate->id = R600_PIPE_STATE_CONFIG;
+
+ /* SQ_CONFIG */
+ tmp = 0;
+ switch (family) {
+ case CHIP_RV610:
+ case CHIP_RV620:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ case CHIP_RV710:
+ break;
+ default:
+ tmp |= S_008C00_VC_ENABLE(1);
+ break;
+ }
+ tmp |= S_008C00_DX9_CONSTS(1);
+ tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+ tmp |= S_008C00_PS_PRIO(ps_prio);
+ tmp |= S_008C00_VS_PRIO(vs_prio);
+ tmp |= S_008C00_GS_PRIO(gs_prio);
+ tmp |= S_008C00_ES_PRIO(es_prio);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
+
+ /* SQ_GPR_RESOURCE_MGMT_1 */
+ tmp = 0;
+ tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+ tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+ tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+ /* SQ_GPR_RESOURCE_MGMT_2 */
+ tmp = 0;
+ tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+ tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+ /* SQ_THREAD_RESOURCE_MGMT */
+ tmp = 0;
+ tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+ tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+ tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+ tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
+
+ /* SQ_STACK_RESOURCE_MGMT_1 */
+ tmp = 0;
+ tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+ tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+ /* SQ_STACK_RESOURCE_MGMT_2 */
+ tmp = 0;
+ tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+ tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
+
+ if (family >= CHIP_RV770) {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
+ } else {
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
+ }
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
+
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, 0x00FFFFFF, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
+ r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
+{
+ struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
+ struct r600_screen* rscreen = (struct r600_screen *)screen;
+
+ if (rctx == NULL)
+ return NULL;
+ rctx->context.winsys = rscreen->screen.winsys;
+ rctx->context.screen = screen;
+ rctx->context.priv = priv;
+ rctx->context.destroy = r600_destroy_context;
+ rctx->context.draw_vbo = r600_draw_vbo2;
+ rctx->context.flush = r600_flush2;
+
+ /* Easy accessing of screen/winsys. */
+ rctx->screen = rscreen;
+ rctx->radeon = rscreen->radeon;
+
+ r600_init_blit_functions2(rctx);
+ r600_init_state_functions2(rctx);
+ r600_init_context_resource_functions2(rctx);
+
+ rctx->blitter = util_blitter_create(&rctx->context);
+ if (rctx->blitter == NULL) {
+ FREE(rctx);
+ return NULL;
+ }
+
+ if (r600_context_init(&rctx->ctx, rctx->radeon)) {
+ r600_destroy_context(&rctx->context);
+ return NULL;
+ }
+
+ r600_init_config2(rctx);
+
+ return &rctx->context;
+}
+
+static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+{
+ switch(shader)
+ {
+ case PIPE_SHADER_FRAGMENT:
+ case PIPE_SHADER_VERTEX:
+ break;
+ case PIPE_SHADER_GEOMETRY:
+ /* TODO: support and enable geometry programs */
+ return 0;
+ default:
+ /* TODO: support tessellation on Evergreen */
+ return 0;
+ }
+
+ /* TODO: all these should be fixed, since r600 surely supports much more! */
+ switch (param) {
+ case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+ case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+ case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+ case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+ return 16384;
+ case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+ return 8; /* FIXME */
+ case PIPE_SHADER_CAP_MAX_INPUTS:
+ if(shader == PIPE_SHADER_FRAGMENT)
+ return 10;
+ else
+ return 16;
+ case PIPE_SHADER_CAP_MAX_TEMPS:
+ return 256; //max native temporaries
+ case PIPE_SHADER_CAP_MAX_ADDRS:
+ return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
+ case PIPE_SHADER_CAP_MAX_CONSTS:
+ return 256; //max native parameters
+ case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+ return 1;
+ case PIPE_SHADER_CAP_MAX_PREDS:
+ return 0; /* FIXME */
+ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+ /* TODO: support this! */
+ return 0;
+ default:
+ return 0;
+ }
+}
+
+void r600_init_screen_texture_functions(struct pipe_screen *screen);
+struct pipe_screen *r600_screen_create2(struct radeon *radeon)
+{
+ struct r600_screen *rscreen;
+ enum radeon_family family = r600_get_family(radeon);
+
+ rscreen = CALLOC_STRUCT(r600_screen);
+ if (rscreen == NULL) {
+ return NULL;
+ }
+
+ switch (family) {
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ rscreen->chip_class = R600;
+ break;
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ rscreen->chip_class = R700;
+ break;
+ default:
+ FREE(rscreen);
+ return NULL;
+ }
+ rscreen->radeon = radeon;
+ rscreen->screen.winsys = (struct pipe_winsys*)radeon;
+ rscreen->screen.destroy = r600_destroy_screen;
+ rscreen->screen.get_name = r600_get_name;
+ rscreen->screen.get_vendor = r600_get_vendor;
+ rscreen->screen.get_param = r600_get_param;
+ rscreen->screen.get_shader_param = r600_get_shader_param;
+ rscreen->screen.get_paramf = r600_get_paramf;
+ rscreen->screen.is_format_supported = r600_is_format_supported;
+ rscreen->screen.context_create = r600_create_context2;
+ r600_init_screen_texture_functions(&rscreen->screen);
+ r600_init_screen_resource_functions(&rscreen->screen);
+
+ return &rscreen->screen;
+}
char *map;
int r;
- r600_flush(ctx, 0, NULL);
+ ctx->flush(ctx, 0, NULL);
if (rtransfer->linear_texture) {
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
} else {
#define S_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) & 0xF) << 28)
#define G_008C04_NUM_CLAUSE_TEMP_GPRS(x) (((x) >> 28) & 0xF)
#define C_008C04_NUM_CLAUSE_TEMP_GPRS(x) 0x0FFFFFFF
-#define R_008C08_SQ_GPR_RESOURCE_MGMT_2 0x00008C08
-#define S_008C08_NUM_GS_GPRS(x) (((x) & 0xFF) << 0)
-#define G_008C08_NUM_GS_GPRS(x) (((x) >> 0) & 0xFF)
-#define C_008C08_NUM_GS_GPRS(x) 0xFFFFFF00
-#define S_008C08_NUM_ES_GPRS(x) (((x) & 0xFF) << 16)
-#define G_008C08_NUM_ES_GPRS(x) (((x) >> 16) & 0xFF)
-#define C_008C08_NUM_ES_GPRS(x) 0xFF00FFFF
#define R_008C0C_SQ_THREAD_RESOURCE_MGMT 0x00008C0C
#define S_008C0C_NUM_PS_THREADS(x) (((x) & 0xFF) << 0)
#define G_008C0C_NUM_PS_THREADS(x) (((x) >> 0) & 0xFF)
#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
+#define R_028414_CB_BLEND_RED 0x028414
+#define S_028414_BLEND_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028414_BLEND_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028414_BLEND_RED 0x00000000
+#define R_028418_CB_BLEND_GREEN 0x028418
+#define S_028418_BLEND_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028418_BLEND_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028418_BLEND_GREEN 0x00000000
+#define R_02841C_CB_BLEND_BLUE 0x02841C
+#define S_02841C_BLEND_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_02841C_BLEND_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_02841C_BLEND_BLUE 0x00000000
+#define R_028420_CB_BLEND_ALPHA 0x028420
+#define S_028420_BLEND_ALPHA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028420_BLEND_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028420_BLEND_ALPHA 0x00000000
#define R_028430_DB_STENCILREFMASK 0x028430
#define S_028430_STENCILREF(x) (((x) & 0xFF) << 0)
#define G_028430_STENCILREF(x) (((x) >> 0) & 0xFF)
#define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16)
#define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF)
#define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF
+#define R_028780_CB_BLEND0_CONTROL 0x028780
+#define R_028784_CB_BLEND1_CONTROL 0x028784
+#define R_028788_CB_BLEND2_CONTROL 0x028788
+#define R_02878C_CB_BLEND3_CONTROL 0x02878C
+#define R_028790_CB_BLEND4_CONTROL 0x028790
+#define R_028794_CB_BLEND5_CONTROL 0x028794
+#define R_028798_CB_BLEND6_CONTROL 0x028798
+#define R_02879C_CB_BLEND7_CONTROL 0x02879C
#define R_028804_CB_BLEND_CONTROL 0x028804
#define S_028804_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0)
#define G_028804_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F)
#define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14)
#define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1)
#define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF
+#define R_028084_CB_COLOR1_VIEW 0x028084
+#define R_028088_CB_COLOR2_VIEW 0x028088
+#define R_02808C_CB_COLOR3_VIEW 0x02808C
+#define R_028090_CB_COLOR4_VIEW 0x028090
+#define R_028094_CB_COLOR5_VIEW 0x028094
+#define R_028098_CB_COLOR6_VIEW 0x028098
+#define R_02809C_CB_COLOR7_VIEW 0x02809C
+#define R_028104_CB_COLOR1_MASK 0x028104
+#define R_028108_CB_COLOR2_MASK 0x028108
+#define R_02810C_CB_COLOR3_MASK 0x02810C
+#define R_028110_CB_COLOR4_MASK 0x028110
+#define R_028114_CB_COLOR5_MASK 0x028114
+#define R_028118_CB_COLOR6_MASK 0x028118
+#define R_02811C_CB_COLOR7_MASK 0x02811C
+#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
+#define R_0280C4_CB_COLOR1_TILE 0x0280C4
+#define R_0280C8_CB_COLOR2_TILE 0x0280C8
+#define R_0280CC_CB_COLOR3_TILE 0x0280CC
+#define R_0280D0_CB_COLOR4_TILE 0x0280D0
+#define R_0280D4_CB_COLOR5_TILE 0x0280D4
+#define R_0280D8_CB_COLOR6_TILE 0x0280D8
+#define R_0280DC_CB_COLOR7_TILE 0x0280DC
+#define R_0280A4_CB_COLOR1_INFO 0x0280A4
+#define R_0280A8_CB_COLOR2_INFO 0x0280A8
+#define R_0280AC_CB_COLOR3_INFO 0x0280AC
+#define R_0280B0_CB_COLOR4_INFO 0x0280B0
+#define R_0280B4_CB_COLOR5_INFO 0x0280B4
+#define R_0280B8_CB_COLOR6_INFO 0x0280B8
+#define R_0280BC_CB_COLOR7_INFO 0x0280BC
+#define R_028C30_CB_CLRCMP_CONTROL 0x028C30
+#define S_028C30_CLRCMP_FCN_SRC(x) (((x) & 0x7) << 0)
+#define G_028C30_CLRCMP_FCN_SRC(x) (((x) >> 0) & 0x7)
+#define C_028C30_CLRCMP_FCN_SRC 0xFFFFFFF8
+#define S_028C30_CLRCMP_FCN_DST(x) (((x) & 0x7) << 8)
+#define G_028C30_CLRCMP_FCN_DST(x) (((x) >> 8) & 0x7)
+#define C_028C30_CLRCMP_FCN_DST 0xFFFFF8FF
+#define S_028C30_CLRCMP_FCN_SEL(x) (((x) & 0x3) << 24)
+#define G_028C30_CLRCMP_FCN_SEL(x) (((x) >> 24) & 0x3)
+#define C_028C30_CLRCMP_FCN_SEL 0xFCFFFFFF
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0x028C20
+#define S_028C20_S4_X(x) (((x) & 0xF) << 0)
+#define G_028C20_S4_X(x) (((x) >> 0) & 0xF)
+#define C_028C20_S4_X 0xFFFFFFF0
+#define S_028C20_S4_Y(x) (((x) & 0xF) << 4)
+#define G_028C20_S4_Y(x) (((x) >> 4) & 0xF)
+#define C_028C20_S4_Y 0xFFFFFF0F
+#define S_028C20_S5_X(x) (((x) & 0xF) << 8)
+#define G_028C20_S5_X(x) (((x) >> 8) & 0xF)
+#define C_028C20_S5_X 0xFFFFF0FF
+#define S_028C20_S5_Y(x) (((x) & 0xF) << 12)
+#define G_028C20_S5_Y(x) (((x) >> 12) & 0xF)
+#define C_028C20_S5_Y 0xFFFF0FFF
+#define S_028C20_S6_X(x) (((x) & 0xF) << 16)
+#define G_028C20_S6_X(x) (((x) >> 16) & 0xF)
+#define C_028C20_S6_X 0xFFF0FFFF
+#define S_028C20_S6_Y(x) (((x) & 0xF) << 20)
+#define G_028C20_S6_Y(x) (((x) >> 20) & 0xF)
+#define C_028C20_S6_Y 0xFF0FFFFF
+#define S_028C20_S7_X(x) (((x) & 0xF) << 24)
+#define G_028C20_S7_X(x) (((x) >> 24) & 0xF)
+#define C_028C20_S7_X 0xF0FFFFFF
+#define S_028C20_S7_Y(x) (((x) & 0xF) << 28)
+#define G_028C20_S7_Y(x) (((x) >> 28) & 0xF)
+#define C_028C20_S7_Y 0x0FFFFFFF
+#define R_0280A0_CB_COLOR0_INFO 0x0280A0
+#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
+#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
+#define C_0280A0_ENDIAN 0xFFFFFFFC
+#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
+#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
+#define C_0280A0_FORMAT 0xFFFFFF03
+#define V_0280A0_COLOR_INVALID 0x00000000
+#define V_0280A0_COLOR_8 0x00000001
+#define V_0280A0_COLOR_4_4 0x00000002
+#define V_0280A0_COLOR_3_3_2 0x00000003
+#define V_0280A0_COLOR_16 0x00000005
+#define V_0280A0_COLOR_16_FLOAT 0x00000006
+#define V_0280A0_COLOR_8_8 0x00000007
+#define V_0280A0_COLOR_5_6_5 0x00000008
+#define V_0280A0_COLOR_6_5_5 0x00000009
+#define V_0280A0_COLOR_1_5_5_5 0x0000000A
+#define V_0280A0_COLOR_4_4_4_4 0x0000000B
+#define V_0280A0_COLOR_5_5_5_1 0x0000000C
+#define V_0280A0_COLOR_32 0x0000000D
+#define V_0280A0_COLOR_32_FLOAT 0x0000000E
+#define V_0280A0_COLOR_16_16 0x0000000F
+#define V_0280A0_COLOR_16_16_FLOAT 0x00000010
+#define V_0280A0_COLOR_8_24 0x00000011
+#define V_0280A0_COLOR_8_24_FLOAT 0x00000012
+#define V_0280A0_COLOR_24_8 0x00000013
+#define V_0280A0_COLOR_24_8_FLOAT 0x00000014
+#define V_0280A0_COLOR_10_11_11 0x00000015
+#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
+#define V_0280A0_COLOR_11_11_10 0x00000017
+#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
+#define V_0280A0_COLOR_2_10_10_10 0x00000019
+#define V_0280A0_COLOR_8_8_8_8 0x0000001A
+#define V_0280A0_COLOR_10_10_10_2 0x0000001B
+#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
+#define V_0280A0_COLOR_32_32 0x0000001D
+#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
+#define V_0280A0_COLOR_16_16_16_16 0x0000001F
+#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
+#define V_0280A0_COLOR_32_32_32_32 0x00000022
+#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
+#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
+#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
+#define C_0280A0_ARRAY_MODE 0xFFFFF0FF
+#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
+#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
+#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
+#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
+#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
+#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
+#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
+#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
+#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
+#define C_0280A0_READ_SIZE 0xFFFF7FFF
+#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
+#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
+#define C_0280A0_COMP_SWAP 0xFFFCFFFF
+#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
+#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
+#define C_0280A0_TILE_MODE 0xFFF3FFFF
+#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
+#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
+#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
+#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
+#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
+#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
+#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
+#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
+#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
+#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
+#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
+#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
+#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
+#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
+#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
+#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
+#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
+#define C_0280A0_ROUND_MODE 0xFDFFFFFF
+#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
+#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
+#define C_0280A0_TILE_COMPACT 0xFBFFFFFF
+#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
+#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
+#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
+#define R_028060_CB_COLOR0_SIZE 0x028060
+#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
+#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
+#define C_028060_PITCH_TILE_MAX 0xFFFFFC00
+#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
+#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
+#define C_028060_SLICE_TILE_MAX 0xC00003FF
+#define R_028800_DB_DEPTH_CONTROL 0x028800
+#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
+#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
+#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
+#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
+#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
+#define C_028800_Z_ENABLE 0xFFFFFFFD
+#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
+#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
+#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
+#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
+#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
+#define C_028800_ZFUNC 0xFFFFFF8F
+#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
+#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
+#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
+#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
+#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
+#define C_028800_STENCILFUNC 0xFFFFF8FF
+#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
+#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
+#define C_028800_STENCILFAIL 0xFFFFC7FF
+#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
+#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
+#define C_028800_STENCILZPASS 0xFFFE3FFF
+#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
+#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
+#define C_028800_STENCILZFAIL 0xFFF1FFFF
+#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
+#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
+#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
+#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
+#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
+#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
+#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
+#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
+#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
+#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
+#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
+#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
+#define R_028010_DB_DEPTH_INFO 0x028010
+#define S_028010_FORMAT(x) (((x) & 0x7) << 0)
+#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
+#define C_028010_FORMAT 0xFFFFFFF8
+#define V_028010_DEPTH_INVALID 0x00000000
+#define V_028010_DEPTH_16 0x00000001
+#define V_028010_DEPTH_X8_24 0x00000002
+#define V_028010_DEPTH_8_24 0x00000003
+#define V_028010_DEPTH_X8_24_FLOAT 0x00000004
+#define V_028010_DEPTH_8_24_FLOAT 0x00000005
+#define V_028010_DEPTH_32_FLOAT 0x00000006
+#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
+#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
+#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
+#define C_028010_READ_SIZE 0xFFFFFFF7
+#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
+#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
+#define C_028010_ARRAY_MODE 0xFFF87FFF
+#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
+#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
+#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
+#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
+#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
+#define C_028010_TILE_COMPACT 0xFBFFFFFF
+#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
+#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
+#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
+#define R_028000_DB_DEPTH_SIZE 0x028000
+#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
+#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
+#define C_028000_PITCH_TILE_MAX 0xFFFFFC00
+#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
+#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
+#define C_028000_SLICE_TILE_MAX 0xC00003FF
+#define R_028004_DB_DEPTH_VIEW 0x028004
+#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
+#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
+#define C_028004_SLICE_START 0xFFFFF800
+#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
+#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
+#define C_028004_SLICE_MAX 0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE 0x028D24
+#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)
+#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
+#define C_028D24_HTILE_WIDTH 0xFFFFFFFE
+#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
+#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
+#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD
+#define S_028D24_LINEAR(x) (((x) & 0x1) << 2)
+#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)
+#define C_028D24_LINEAR 0xFFFFFFFB
+#define S_028D24_FULL_CACHE(x) (((x) & 0x1) << 3)
+#define G_028D24_FULL_CACHE(x) (((x) >> 3) & 0x1)
+#define C_028D24_FULL_CACHE 0xFFFFFFF7
+#define S_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 4)
+#define G_028D24_HTILE_USES_PRELOAD_WIN(x) (((x) >> 4) & 0x1)
+#define C_028D24_HTILE_USES_PRELOAD_WIN 0xFFFFFFEF
+#define S_028D24_PRELOAD(x) (((x) & 0x1) << 5)
+#define G_028D24_PRELOAD(x) (((x) >> 5) & 0x1)
+#define C_028D24_PRELOAD 0xFFFFFFDF
+#define S_028D24_PREFETCH_WIDTH(x) (((x) & 0x3F) << 6)
+#define G_028D24_PREFETCH_WIDTH(x) (((x) >> 6) & 0x3F)
+#define C_028D24_PREFETCH_WIDTH 0xFFFFF03F
+#define S_028D24_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 12)
+#define G_028D24_PREFETCH_HEIGHT(x) (((x) >> 12) & 0x3F)
+#define C_028D24_PREFETCH_HEIGHT 0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT 0x028D34
+#define S_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x3FF) << 0)
+#define G_028D34_DEPTH_HEIGHT_TILE_MAX(x) (((x) >> 0) & 0x3FF)
+#define C_028D34_DEPTH_HEIGHT_TILE_MAX 0xFFFFFC00
+#define R_028D10_DB_RENDER_OVERRIDE 0x028D10
+#define S_028D10_FORCE_HIZ_ENABLE(x) (((x) & 0x3) << 0)
+#define G_028D10_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x3)
+#define C_028D10_FORCE_HIZ_ENABLE 0xFFFFFFFC
+#define S_028D10_FORCE_HIS_ENABLE0(x) (((x) & 0x3) << 2)
+#define G_028D10_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x3)
+#define C_028D10_FORCE_HIS_ENABLE0 0xFFFFFFF3
+#define S_028D10_FORCE_HIS_ENABLE1(x) (((x) & 0x3) << 4)
+#define G_028D10_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x3)
+#define C_028D10_FORCE_HIS_ENABLE1 0xFFFFFFCF
+#define S_028D10_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6)
+#define G_028D10_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1)
+#define C_028D10_FORCE_SHADER_Z_ORDER 0xFFFFFFBF
+#define S_028D10_FAST_Z_DISABLE(x) (((x) & 0x1) << 7)
+#define G_028D10_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1)
+#define C_028D10_FAST_Z_DISABLE 0xFFFFFF7F
+#define S_028D10_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8)
+#define G_028D10_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1)
+#define C_028D10_FAST_STENCIL_DISABLE 0xFFFFFEFF
+#define S_028D10_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9)
+#define G_028D10_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1)
+#define C_028D10_NOOP_CULL_DISABLE 0xFFFFFDFF
+#define S_028D10_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10)
+#define G_028D10_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1)
+#define C_028D10_FORCE_COLOR_KILL 0xFFFFFBFF
+#define S_028D10_FORCE_Z_READ(x) (((x) & 0x1) << 11)
+#define G_028D10_FORCE_Z_READ(x) (((x) >> 11) & 0x1)
+#define C_028D10_FORCE_Z_READ 0xFFFFF7FF
+#define S_028D10_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12)
+#define G_028D10_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1)
+#define C_028D10_FORCE_STENCIL_READ 0xFFFFEFFF
+#define S_028D10_FORCE_FULL_Z_RANGE(x) (((x) & 0x3) << 13)
+#define G_028D10_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x3)
+#define C_028D10_FORCE_FULL_Z_RANGE 0xFFFF9FFF
+#define S_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15)
+#define G_028D10_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1)
+#define C_028D10_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF
+#define S_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16)
+#define G_028D10_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1)
+#define C_028D10_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF
+#define S_028D10_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17)
+#define G_028D10_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1)
+#define C_028D10_IGNORE_SC_ZRANGE 0xFFFDFFFF
+#define R_028A40_VGT_GS_MODE 0x028A40
+#define S_028A40_MODE(x) (((x) & 0x3) << 0)
+#define G_028A40_MODE(x) (((x) >> 0) & 0x3)
+#define C_028A40_MODE 0xFFFFFFFC
+#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2)
+#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1)
+#define C_028A40_ES_PASSTHRU 0xFFFFFFFB
+#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3)
+#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3)
+#define C_028A40_CUT_MODE 0xFFFFFFE7
+#define R_008DFC_SQ_CF_WORD0 0x008DFC
+#define S_008DFC_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_008DFC_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_008DFC_ADDR 0x00000000
+#define R_008DFC_SQ_CF_WORD1 0x008DFC
+#define S_008DFC_POP_COUNT(x) (((x) & 0x7) << 0)
+#define G_008DFC_POP_COUNT(x) (((x) >> 0) & 0x7)
+#define C_008DFC_POP_COUNT 0xFFFFFFF8
+#define S_008DFC_CF_CONST(x) (((x) & 0x1F) << 3)
+#define G_008DFC_CF_CONST(x) (((x) >> 3) & 0x1F)
+#define C_008DFC_CF_CONST 0xFFFFFF07
+#define S_008DFC_COND(x) (((x) & 0x3) << 8)
+#define G_008DFC_COND(x) (((x) >> 8) & 0x3)
+#define C_008DFC_COND 0xFFFFFCFF
+#define S_008DFC_COUNT(x) (((x) & 0x7) << 10)
+#define G_008DFC_COUNT(x) (((x) >> 10) & 0x7)
+#define C_008DFC_COUNT 0xFFFFE3FF
+#define S_008DFC_CALL_COUNT(x) (((x) & 0x3F) << 13)
+#define G_008DFC_CALL_COUNT(x) (((x) >> 13) & 0x3F)
+#define C_008DFC_CALL_COUNT 0xFFF81FFF
+#define S_008DFC_END_OF_PROGRAM(x) (((x) & 0x1) << 21)
+#define G_008DFC_END_OF_PROGRAM(x) (((x) >> 21) & 0x1)
+#define C_008DFC_END_OF_PROGRAM 0xFFDFFFFF
+#define S_008DFC_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22)
+#define G_008DFC_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1)
+#define C_008DFC_VALID_PIXEL_MODE 0xFFBFFFFF
+#define S_008DFC_CF_INST(x) (((x) & 0x7F) << 23)
+#define G_008DFC_CF_INST(x) (((x) >> 23) & 0x7F)
+#define C_008DFC_CF_INST 0xC07FFFFF
+#define V_008DFC_SQ_CF_INST_NOP 0x00000000
+#define V_008DFC_SQ_CF_INST_TEX 0x00000001
+#define V_008DFC_SQ_CF_INST_VTX 0x00000002
+#define V_008DFC_SQ_CF_INST_VTX_TC 0x00000003
+#define V_008DFC_SQ_CF_INST_LOOP_START 0x00000004
+#define V_008DFC_SQ_CF_INST_LOOP_END 0x00000005
+#define V_008DFC_SQ_CF_INST_LOOP_START_DX10 0x00000006
+#define V_008DFC_SQ_CF_INST_LOOP_START_NO_AL 0x00000007
+#define V_008DFC_SQ_CF_INST_LOOP_CONTINUE 0x00000008
+#define V_008DFC_SQ_CF_INST_LOOP_BREAK 0x00000009
+#define V_008DFC_SQ_CF_INST_JUMP 0x0000000A
+#define V_008DFC_SQ_CF_INST_PUSH 0x0000000B
+#define V_008DFC_SQ_CF_INST_PUSH_ELSE 0x0000000C
+#define V_008DFC_SQ_CF_INST_ELSE 0x0000000D
+#define V_008DFC_SQ_CF_INST_POP 0x0000000E
+#define V_008DFC_SQ_CF_INST_POP_JUMP 0x0000000F
+#define V_008DFC_SQ_CF_INST_POP_PUSH 0x00000010
+#define V_008DFC_SQ_CF_INST_POP_PUSH_ELSE 0x00000011
+#define V_008DFC_SQ_CF_INST_CALL 0x00000012
+#define V_008DFC_SQ_CF_INST_CALL_FS 0x00000013
+#define V_008DFC_SQ_CF_INST_RETURN 0x00000014
+#define V_008DFC_SQ_CF_INST_EMIT_VERTEX 0x00000015
+#define V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX 0x00000016
+#define V_008DFC_SQ_CF_INST_CUT_VERTEX 0x00000017
+#define V_008DFC_SQ_CF_INST_KILL 0x00000018
+#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30)
+#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1)
+#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF
+#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31)
+#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1)
+#define C_008DFC_BARRIER 0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD0 0x008DFC
+#define S_008DFC_ALU_ADDR(x) (((x) & 0x3FFFFF) << 0)
+#define G_008DFC_ALU_ADDR(x) (((x) >> 0) & 0x3FFFFF)
+#define C_008DFC_ALU_ADDR 0xFFC00000
+#define S_008DFC_KCACHE_BANK0(x) (((x) & 0xF) << 22)
+#define G_008DFC_KCACHE_BANK0(x) (((x) >> 22) & 0xF)
+#define C_008DFC_KCACHE_BANK0 0xFC3FFFFF
+#define S_008DFC_KCACHE_BANK1(x) (((x) & 0xF) << 26)
+#define G_008DFC_KCACHE_BANK1(x) (((x) >> 26) & 0xF)
+#define C_008DFC_KCACHE_BANK1 0xC3FFFFFF
+#define S_008DFC_KCACHE_MODE0(x) (((x) & 0x3) << 30)
+#define G_008DFC_KCACHE_MODE0(x) (((x) >> 30) & 0x3)
+#define C_008DFC_KCACHE_MODE0 0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD1 0x008DFC
+#define S_008DFC_KCACHE_MODE1(x) (((x) & 0x3) << 0)
+#define G_008DFC_KCACHE_MODE1(x) (((x) >> 0) & 0x3)
+#define C_008DFC_KCACHE_MODE1 0xFFFFFFFC
+#define S_008DFC_KCACHE_ADDR0(x) (((x) & 0xFF) << 2)
+#define G_008DFC_KCACHE_ADDR0(x) (((x) >> 2) & 0xFF)
+#define C_008DFC_KCACHE_ADDR0 0xFFFFFC03
+#define S_008DFC_KCACHE_ADDR1(x) (((x) & 0xFF) << 10)
+#define G_008DFC_KCACHE_ADDR1(x) (((x) >> 10) & 0xFF)
+#define C_008DFC_KCACHE_ADDR1 0xFFFC03FF
+#define S_008DFC_ALU_COUNT(x) (((x) & 0x7F) << 18)
+#define G_008DFC_ALU_COUNT(x) (((x) >> 18) & 0x7F)
+#define C_008DFC_ALU_COUNT 0xFE03FFFF
+#define S_008DFC_USES_WATERFALL(x) (((x) & 0x1) << 25)
+#define G_008DFC_USES_WATERFALL(x) (((x) >> 25) & 0x1)
+#define C_008DFC_USES_WATERFALL 0xFDFFFFFF
+#define S_008DFC_CF_ALU_INST(x) (((x) & 0xF) << 26)
+#define G_008DFC_CF_ALU_INST(x) (((x) >> 26) & 0xF)
+#define C_008DFC_CF_ALU_INST 0xC3FFFFFF
+#define V_008DFC_SQ_CF_INST_ALU 0x00000008
+#define V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE 0x00000009
+#define V_008DFC_SQ_CF_INST_ALU_POP_AFTER 0x0000000A
+#define V_008DFC_SQ_CF_INST_ALU_POP2_AFTER 0x0000000B
+#define V_008DFC_SQ_CF_INST_ALU_CONTINUE 0x0000000D
+#define V_008DFC_SQ_CF_INST_ALU_BREAK 0x0000000E
+#define V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER 0x0000000F
+#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30)
+#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1)
+#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF
+#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31)
+#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1)
+#define C_008DFC_BARRIER 0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0 0x008DFC
+#define S_008DFC_ARRAY_BASE(x) (((x) & 0x1FFF) << 0)
+#define G_008DFC_ARRAY_BASE(x) (((x) >> 0) & 0x1FFF)
+#define C_008DFC_ARRAY_BASE 0xFFFFE000
+#define S_008DFC_TYPE(x) (((x) & 0x3) << 13)
+#define G_008DFC_TYPE(x) (((x) >> 13) & 0x3)
+#define C_008DFC_TYPE 0xFFFF9FFF
+#define S_008DFC_RW_GPR(x) (((x) & 0x7F) << 15)
+#define G_008DFC_RW_GPR(x) (((x) >> 15) & 0x7F)
+#define C_008DFC_RW_GPR 0xFFC07FFF
+#define S_008DFC_RW_REL(x) (((x) & 0x1) << 22)
+#define G_008DFC_RW_REL(x) (((x) >> 22) & 0x1)
+#define C_008DFC_RW_REL 0xFFBFFFFF
+#define S_008DFC_INDEX_GPR(x) (((x) & 0x7F) << 23)
+#define G_008DFC_INDEX_GPR(x) (((x) >> 23) & 0x7F)
+#define C_008DFC_INDEX_GPR 0xC07FFFFF
+#define S_008DFC_ELEM_SIZE(x) (((x) & 0x3) << 30)
+#define G_008DFC_ELEM_SIZE(x) (((x) >> 30) & 0x3)
+#define C_008DFC_ELEM_SIZE 0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1 0x008DFC
+#define S_008DFC_BURST_COUNT(x) (((x) & 0xF) << 17)
+#define G_008DFC_BURST_COUNT(x) (((x) >> 17) & 0xF)
+#define C_008DFC_BURST_COUNT 0xFFE1FFFF
+#define S_008DFC_END_OF_PROGRAM(x) (((x) & 0x1) << 21)
+#define G_008DFC_END_OF_PROGRAM(x) (((x) >> 21) & 0x1)
+#define C_008DFC_END_OF_PROGRAM 0xFFDFFFFF
+#define S_008DFC_VALID_PIXEL_MODE(x) (((x) & 0x1) << 22)
+#define G_008DFC_VALID_PIXEL_MODE(x) (((x) >> 22) & 0x1)
+#define C_008DFC_VALID_PIXEL_MODE 0xFFBFFFFF
+#define S_008DFC_CF_INST(x) (((x) & 0x7F) << 23)
+#define G_008DFC_CF_INST(x) (((x) >> 23) & 0x7F)
+#define C_008DFC_CF_INST 0xC07FFFFF
+#define V_008DFC_SQ_CF_INST_MEM_STREAM0 0x00000020
+#define V_008DFC_SQ_CF_INST_MEM_STREAM1 0x00000021
+#define V_008DFC_SQ_CF_INST_MEM_STREAM2 0x00000022
+#define V_008DFC_SQ_CF_INST_MEM_STREAM3 0x00000023
+#define V_008DFC_SQ_CF_INST_MEM_SCRATCH 0x00000024
+#define V_008DFC_SQ_CF_INST_MEM_REDUCTION 0x00000025
+#define V_008DFC_SQ_CF_INST_MEM_RING 0x00000026
+#define V_008DFC_SQ_CF_INST_EXPORT 0x00000027
+#define V_008DFC_SQ_CF_INST_EXPORT_DONE 0x00000028
+#define S_008DFC_WHOLE_QUAD_MODE(x) (((x) & 0x1) << 30)
+#define G_008DFC_WHOLE_QUAD_MODE(x) (((x) >> 30) & 0x1)
+#define C_008DFC_WHOLE_QUAD_MODE 0xBFFFFFFF
+#define S_008DFC_BARRIER(x) (((x) & 0x1) << 31)
+#define G_008DFC_BARRIER(x) (((x) >> 31) & 0x1)
+#define C_008DFC_BARRIER 0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF 0x008DFC
+#define S_008DFC_ARRAY_SIZE(x) (((x) & 0xFFF) << 0)
+#define G_008DFC_ARRAY_SIZE(x) (((x) >> 0) & 0xFFF)
+#define C_008DFC_ARRAY_SIZE 0xFFFFF000
+#define S_008DFC_COMP_MASK(x) (((x) & 0xF) << 12)
+#define G_008DFC_COMP_MASK(x) (((x) >> 12) & 0xF)
+#define C_008DFC_COMP_MASK 0xFFFF0FFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ 0x008DFC
+#define S_008DFC_SEL_X(x) (((x) & 0x7) << 0)
+#define G_008DFC_SEL_X(x) (((x) >> 0) & 0x7)
+#define C_008DFC_SEL_X 0xFFFFFFF8
+#define S_008DFC_SEL_Y(x) (((x) & 0x7) << 3)
+#define G_008DFC_SEL_Y(x) (((x) >> 3) & 0x7)
+#define C_008DFC_SEL_Y 0xFFFFFFC7
+#define S_008DFC_SEL_Z(x) (((x) & 0x7) << 6)
+#define G_008DFC_SEL_Z(x) (((x) >> 6) & 0x7)
+#define C_008DFC_SEL_Z 0xFFFFFE3F
+#define S_008DFC_SEL_W(x) (((x) & 0x7) << 9)
+#define G_008DFC_SEL_W(x) (((x) >> 9) & 0x7)
+#define C_008DFC_SEL_W 0xFFFFF1FF
+#define R_008DFC_SQ_VTX_WORD0 0x008DFC
+#define S_008DFC_VTX_INST(x) (((x) & 0x1F) << 0)
+#define G_008DFC_VTX_INST(x) (((x) >> 0) & 0x1F)
+#define C_008DFC_VTX_INST 0xFFFFFFE0
+#define S_008DFC_FETCH_TYPE(x) (((x) & 0x3) << 5)
+#define G_008DFC_FETCH_TYPE(x) (((x) >> 5) & 0x3)
+#define C_008DFC_FETCH_TYPE 0xFFFFFF9F
+#define S_008DFC_FETCH_WHOLE_QUAD(x) (((x) & 0x1) << 7)
+#define G_008DFC_FETCH_WHOLE_QUAD(x) (((x) >> 7) & 0x1)
+#define C_008DFC_FETCH_WHOLE_QUAD 0xFFFFFF7F
+#define S_008DFC_BUFFER_ID(x) (((x) & 0xFF) << 8)
+#define G_008DFC_BUFFER_ID(x) (((x) >> 8) & 0xFF)
+#define C_008DFC_BUFFER_ID 0xFFFF00FF
+#define S_008DFC_SRC_GPR(x) (((x) & 0x7F) << 16)
+#define G_008DFC_SRC_GPR(x) (((x) >> 16) & 0x7F)
+#define C_008DFC_SRC_GPR 0xFF80FFFF
+#define S_008DFC_SRC_REL(x) (((x) & 0x1) << 23)
+#define G_008DFC_SRC_REL(x) (((x) >> 23) & 0x1)
+#define C_008DFC_SRC_REL 0xFF7FFFFF
+#define S_008DFC_SRC_SEL_X(x) (((x) & 0x3) << 24)
+#define G_008DFC_SRC_SEL_X(x) (((x) >> 24) & 0x3)
+#define C_008DFC_SRC_SEL_X 0xFCFFFFFF
+#define S_008DFC_MEGA_FETCH_COUNT(x) (((x) & 0x3F) << 26)
+#define G_008DFC_MEGA_FETCH_COUNT(x) (((x) >> 26) & 0x3F)
+#define C_008DFC_MEGA_FETCH_COUNT 0x03FFFFFF
+#define R_008DFC_SQ_VTX_WORD1 0x008DFC
+#define S_008DFC_DST_SEL_X(x) (((x) & 0x7) << 9)
+#define G_008DFC_DST_SEL_X(x) (((x) >> 9) & 0x7)
+#define C_008DFC_DST_SEL_X 0xFFFFF1FF
+#define S_008DFC_DST_SEL_Y(x) (((x) & 0x7) << 12)
+#define G_008DFC_DST_SEL_Y(x) (((x) >> 12) & 0x7)
+#define C_008DFC_DST_SEL_Y 0xFFFF8FFF
+#define S_008DFC_DST_SEL_Z(x) (((x) & 0x7) << 15)
+#define G_008DFC_DST_SEL_Z(x) (((x) >> 15) & 0x7)
+#define C_008DFC_DST_SEL_Z 0xFFFC7FFF
+#define S_008DFC_DST_SEL_W(x) (((x) & 0x7) << 18)
+#define G_008DFC_DST_SEL_W(x) (((x) >> 18) & 0x7)
+#define C_008DFC_DST_SEL_W 0xFFE3FFFF
+#define S_008DFC_USE_CONST_FIELDS(x) (((x) & 0x1) << 21)
+#define G_008DFC_USE_CONST_FIELDS(x) (((x) >> 21) & 0x1)
+#define C_008DFC_USE_CONST_FIELDS 0xFFDFFFFF
+#define S_008DFC_DATA_FORMAT(x) (((x) & 0x3F) << 22)
+#define G_008DFC_DATA_FORMAT(x) (((x) >> 22) & 0x3F)
+#define C_008DFC_DATA_FORMAT 0xF03FFFFF
+#define S_008DFC_NUM_FORMAT_ALL(x) (((x) & 0x3) << 28)
+#define G_008DFC_NUM_FORMAT_ALL(x) (((x) >> 28) & 0x3)
+#define C_008DFC_NUM_FORMAT_ALL 0xCFFFFFFF
+#define S_008DFC_FORMAT_COMP_ALL(x) (((x) & 0x1) << 30)
+#define G_008DFC_FORMAT_COMP_ALL(x) (((x) >> 30) & 0x1)
+#define C_008DFC_FORMAT_COMP_ALL 0xBFFFFFFF
+#define S_008DFC_SRF_MODE_ALL(x) (((x) & 0x1) << 31)
+#define G_008DFC_SRF_MODE_ALL(x) (((x) >> 31) & 0x1)
+#define C_008DFC_SRF_MODE_ALL 0x7FFFFFFF
+#define R_008DFC_SQ_VTX_WORD1_GPR 0x008DFC
+#define S_008DFC_DST_GPR(x) (((x) & 0x7F) << 0)
+#define G_008DFC_DST_GPR(x) (((x) >> 0) & 0x7F)
+#define C_008DFC_DST_GPR 0xFFFFFF80
+#define S_008DFC_DST_REL(x) (((x) & 0x1) << 7)
+#define G_008DFC_DST_REL(x) (((x) >> 7) & 0x1)
+#define C_008DFC_DST_REL 0xFFFFFF7F
+#define R_008DFC_SQ_VTX_WORD2 0x008DFC
+#define S_008DFC_OFFSET(x) (((x) & 0xFFFF) << 0)
+#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFFF)
+#define C_008DFC_OFFSET 0xFFFF0000
+#define S_008DFC_ENDIAN_SWAP(x) (((x) & 0x3) << 16)
+#define G_008DFC_ENDIAN_SWAP(x) (((x) >> 16) & 0x3)
+#define C_008DFC_ENDIAN_SWAP 0xFFFCFFFF
+#define S_008DFC_CONST_BUF_NO_STRIDE(x) (((x) & 0x1) << 18)
+#define G_008DFC_CONST_BUF_NO_STRIDE(x) (((x) >> 18) & 0x1)
+#define C_008DFC_CONST_BUF_NO_STRIDE 0xFFFBFFFF
+#define S_008DFC_MEGA_FETCH(x) (((x) & 0x1) << 19)
+#define G_008DFC_MEGA_FETCH(x) (((x) >> 19) & 0x1)
+#define C_008DFC_MEGA_FETCH 0xFFF7FFFF
+#define S_008DFC_ALT_CONST(x) (((x) & 0x1) << 20)
+#define G_008DFC_ALT_CONST(x) (((x) >> 20) & 0x1)
+#define C_008DFC_ALT_CONST 0xFFEFFFFF
+#define R_008040_WAIT_UNTIL 0x008040
+#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8)
+#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1)
+#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF
+#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10)
+#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1)
+#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF
+#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14)
+#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1)
+#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF
+#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15)
+#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1)
+#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF
+#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16)
+#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1)
+#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF
+#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17)
+#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1)
+#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF
+#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19)
+#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1)
+#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF
+#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20)
+#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F)
+#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF
+#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC
+#define S_0286CC_NUM_INTERP(x) (((x) & 0x3F) << 0)
+#define G_0286CC_NUM_INTERP(x) (((x) >> 0) & 0x3F)
+#define C_0286CC_NUM_INTERP 0xFFFFFFC0
+#define S_0286CC_POSITION_ENA(x) (((x) & 0x1) << 8)
+#define G_0286CC_POSITION_ENA(x) (((x) >> 8) & 0x1)
+#define C_0286CC_POSITION_ENA 0xFFFFFEFF
+#define S_0286CC_POSITION_CENTROID(x) (((x) & 0x1) << 9)
+#define G_0286CC_POSITION_CENTROID(x) (((x) >> 9) & 0x1)
+#define C_0286CC_POSITION_CENTROID 0xFFFFFDFF
+#define S_0286CC_POSITION_ADDR(x) (((x) & 0x1F) << 10)
+#define G_0286CC_POSITION_ADDR(x) (((x) >> 10) & 0x1F)
+#define C_0286CC_POSITION_ADDR 0xFFFF83FF
+#define S_0286CC_PARAM_GEN(x) (((x) & 0xF) << 15)
+#define G_0286CC_PARAM_GEN(x) (((x) >> 15) & 0xF)
+#define C_0286CC_PARAM_GEN 0xFFF87FFF
+#define S_0286CC_PARAM_GEN_ADDR(x) (((x) & 0x7F) << 19)
+#define G_0286CC_PARAM_GEN_ADDR(x) (((x) >> 19) & 0x7F)
+#define C_0286CC_PARAM_GEN_ADDR 0xFC07FFFF
+#define S_0286CC_BARYC_SAMPLE_CNTL(x) (((x) & 0x3) << 26)
+#define G_0286CC_BARYC_SAMPLE_CNTL(x) (((x) >> 26) & 0x3)
+#define C_0286CC_BARYC_SAMPLE_CNTL 0xF3FFFFFF
+#define S_0286CC_PERSP_GRADIENT_ENA(x) (((x) & 0x1) << 28)
+#define G_0286CC_PERSP_GRADIENT_ENA(x) (((x) >> 28) & 0x1)
+#define C_0286CC_PERSP_GRADIENT_ENA 0xEFFFFFFF
+#define S_0286CC_LINEAR_GRADIENT_ENA(x) (((x) & 0x1) << 29)
+#define G_0286CC_LINEAR_GRADIENT_ENA(x) (((x) >> 29) & 0x1)
+#define C_0286CC_LINEAR_GRADIENT_ENA 0xDFFFFFFF
+#define S_0286CC_POSITION_SAMPLE(x) (((x) & 0x1) << 30)
+#define G_0286CC_POSITION_SAMPLE(x) (((x) >> 30) & 0x1)
+#define C_0286CC_POSITION_SAMPLE 0xBFFFFFFF
+#define S_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) & 0x1) << 31)
+#define G_0286CC_BARYC_AT_SAMPLE_ENA(x) (((x) >> 31) & 0x1)
+#define C_0286CC_BARYC_AT_SAMPLE_ENA 0x7FFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0
+#define S_0286D0_GEN_INDEX_PIX(x) (((x) & 0x1) << 0)
+#define G_0286D0_GEN_INDEX_PIX(x) (((x) >> 0) & 0x1)
+#define C_0286D0_GEN_INDEX_PIX 0xFFFFFFFE
+#define S_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) & 0x7F) << 1)
+#define G_0286D0_GEN_INDEX_PIX_ADDR(x) (((x) >> 1) & 0x7F)
+#define C_0286D0_GEN_INDEX_PIX_ADDR 0xFFFFFF01
+#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 8)
+#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 8) & 0x1)
+#define C_0286D0_FRONT_FACE_ENA 0xFFFFFEFF
+#define S_0286D0_FRONT_FACE_CHAN(x) (((x) & 0x3) << 9)
+#define G_0286D0_FRONT_FACE_CHAN(x) (((x) >> 9) & 0x3)
+#define C_0286D0_FRONT_FACE_CHAN 0xFFFFF9FF
+#define S_0286D0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 11)
+#define G_0286D0_FRONT_FACE_ALL_BITS(x) (((x) >> 11) & 0x1)
+#define C_0286D0_FRONT_FACE_ALL_BITS 0xFFFFF7FF
+#define S_0286D0_FRONT_FACE_ADDR(x) (((x) & 0x1F) << 12)
+#define G_0286D0_FRONT_FACE_ADDR(x) (((x) >> 12) & 0x1F)
+#define C_0286D0_FRONT_FACE_ADDR 0xFFFE0FFF
+#define S_0286D0_FOG_ADDR(x) (((x) & 0x7F) << 17)
+#define G_0286D0_FOG_ADDR(x) (((x) >> 17) & 0x7F)
+#define C_0286D0_FOG_ADDR 0xFF01FFFF
+#define S_0286D0_FIXED_PT_POSITION_ENA(x) (((x) & 0x1) << 24)
+#define G_0286D0_FIXED_PT_POSITION_ENA(x) (((x) >> 24) & 0x1)
+#define C_0286D0_FIXED_PT_POSITION_ENA 0xFEFFFFFF
+#define S_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) & 0x1F) << 25)
+#define G_0286D0_FIXED_PT_POSITION_ADDR(x) (((x) >> 25) & 0x1F)
+#define C_0286D0_FIXED_PT_POSITION_ADDR 0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4
+#define S_0286C4_VS_PER_COMPONENT(x) (((x) & 0x1) << 0)
+#define G_0286C4_VS_PER_COMPONENT(x) (((x) >> 0) & 0x1)
+#define C_0286C4_VS_PER_COMPONENT 0xFFFFFFFE
+#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1)
+#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F)
+#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1
+#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 8)
+#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 8) & 0x1)
+#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFEFF
+#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 9)
+#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 9) & 0x1F)
+#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFC1FF
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240
+#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0)
+#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028240_TL_X 0xFFFFC000
+#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028240_TL_Y 0xC000FFFF
+#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
+#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
+#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244
+#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0)
+#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028244_BR_X 0xFFFFC000
+#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028244_BR_Y 0xC000FFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030
+#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0)
+#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF)
+#define C_028030_TL_X 0xFFFF8000
+#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16)
+#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF)
+#define C_028030_TL_Y 0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034
+#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0)
+#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF)
+#define C_028034_BR_X 0xFFFF8000
+#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16)
+#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF)
+#define C_028034_BR_Y 0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204
+#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0)
+#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028204_TL_X 0xFFFFC000
+#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028204_TL_Y 0xC000FFFF
+#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
+#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
+#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208
+#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0)
+#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028208_BR_X 0xFFFFC000
+#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028208_BR_Y 0xC000FFFF
+#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0
+#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x3) << 0)
+#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x3)
+#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC
+#define S_0287F0_MAJOR_MODE(x) (((x) & 0x3) << 2)
+#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x3)
+#define C_0287F0_MAJOR_MODE 0xFFFFFFF3
+#define S_0287F0_SPRITE_EN(x) (((x) & 0x1) << 4)
+#define G_0287F0_SPRITE_EN(x) (((x) >> 4) & 0x1)
+#define C_0287F0_SPRITE_EN 0xFFFFFFEF
+#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5)
+#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1)
+#define C_0287F0_NOT_EOP 0xFFFFFFDF
+#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6)
+#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1)
+#define C_0287F0_USE_OPAQUE 0xFFFFFFBF
+#define R_0280A0_CB_COLOR0_INFO 0x0280A0
+#define R_0280A4_CB_COLOR1_INFO 0x0280A4
+#define R_0280A8_CB_COLOR2_INFO 0x0280A8
+#define R_0280AC_CB_COLOR3_INFO 0x0280AC
+#define R_0280B0_CB_COLOR4_INFO 0x0280B0
+#define R_0280B4_CB_COLOR5_INFO 0x0280B4
+#define R_0280B8_CB_COLOR6_INFO 0x0280B8
+#define R_0280BC_CB_COLOR7_INFO 0x0280BC
+#define R_02800C_DB_DEPTH_BASE 0x02800C
+#define R_028000_DB_DEPTH_SIZE 0x028000
+#define R_028004_DB_DEPTH_VIEW 0x028004
+#define R_028010_DB_DEPTH_INFO 0x028010
+#define R_028D24_DB_HTILE_SURFACE 0x028D24
+#define R_028D34_DB_PREFETCH_LIMIT 0x028D34
+#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4
+#define R_028A48_PA_SC_MPASS_PS_CNTL 0x028A48
+#define R_028C00_PA_SC_LINE_CNTL 0x028C00
+#define R_028C04_PA_SC_AA_CONFIG 0x028C04
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C
+#define R_028C48_PA_SC_AA_MASK 0x028C48
+#define R_028810_PA_CL_CLIP_CNTL 0x028810
+#define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C
+#define R_028820_PA_CL_NANINF_CNTL 0x028820
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ 0x028C18
+#define R_028814_PA_SU_SC_MODE_CNTL 0x028814
+#define R_028A00_PA_SU_POINT_SIZE 0x028A00
+#define R_028A04_PA_SU_POINT_MINMAX 0x028A04
+#define R_028A08_PA_SU_LINE_CNTL 0x028A08
+#define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028DF8
+#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP 0x028DFC
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028E00
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028E04
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE 0x028E08
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028E0C
+#define R_028818_PA_CL_VTE_CNTL 0x028818
+#define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C
+#define R_028444_PA_CL_VPORT_YSCALE_0 0x028444
+#define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C
+#define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440
+#define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448
+#define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254
+#define R_028780_CB_BLEND0_CONTROL 0x028780
+#define R_028784_CB_BLEND1_CONTROL 0x028784
+#define R_028788_CB_BLEND2_CONTROL 0x028788
+#define R_02878C_CB_BLEND3_CONTROL 0x02878C
+#define R_028790_CB_BLEND4_CONTROL 0x028790
+#define R_028794_CB_BLEND5_CONTROL 0x028794
+#define R_028798_CB_BLEND6_CONTROL 0x028798
+#define R_02879C_CB_BLEND7_CONTROL 0x02879C
+#define R_028804_CB_BLEND_CONTROL 0x028804
+#define R_028028_DB_STENCIL_CLEAR 0x028028
+#define R_02802C_DB_DEPTH_CLEAR 0x02802C
+#define R_028430_DB_STENCILREFMASK 0x028430
+#define R_028434_DB_STENCILREFMASK_BF 0x028434
+#define R_028800_DB_DEPTH_CONTROL 0x028800
+#define R_02880C_DB_SHADER_CONTROL 0x02880C
+#define R_028D0C_DB_RENDER_CONTROL 0x028D0C
+#define R_028D10_DB_RENDER_OVERRIDE 0x028D10
+#define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C
+#define R_028D30_DB_PRELOAD_CONTROL 0x028D30
+#define R_028D44_DB_ALPHA_TO_MASK 0x028D44
+#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
+#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC
+#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0
+#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644
+#define R_028648_SPI_PS_INPUT_CNTL_1 0x028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C
+#define R_028650_SPI_PS_INPUT_CNTL_3 0x028650
+#define R_028654_SPI_PS_INPUT_CNTL_4 0x028654
+#define R_028658_SPI_PS_INPUT_CNTL_5 0x028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C
+#define R_028660_SPI_PS_INPUT_CNTL_7 0x028660
+#define R_028664_SPI_PS_INPUT_CNTL_8 0x028664
+#define R_028668_SPI_PS_INPUT_CNTL_9 0x028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C
+#define R_028670_SPI_PS_INPUT_CNTL_11 0x028670
+#define R_028674_SPI_PS_INPUT_CNTL_12 0x028674
+#define R_028678_SPI_PS_INPUT_CNTL_13 0x028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C
+#define R_028680_SPI_PS_INPUT_CNTL_15 0x028680
+#define R_028684_SPI_PS_INPUT_CNTL_16 0x028684
+#define R_028688_SPI_PS_INPUT_CNTL_17 0x028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C
+#define R_028690_SPI_PS_INPUT_CNTL_19 0x028690
+#define R_028694_SPI_PS_INPUT_CNTL_20 0x028694
+#define R_028698_SPI_PS_INPUT_CNTL_21 0x028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0
+#define R_028850_SQ_PGM_RESOURCES_PS 0x028850
+#define R_028854_SQ_PGM_EXPORTS_PS 0x028854
+#define R_008958_VGT_PRIMITIVE_TYPE 0x008958
+#define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C
+#define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88
+#define R_008970_VGT_NUM_INDICES 0x008970
+#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0
+#define R_028238_CB_TARGET_MASK 0x028238
+#define R_02823C_CB_SHADER_MASK 0x02823C
+#define R_028060_CB_COLOR0_SIZE 0x028060
+#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
+#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
+#define C_028060_PITCH_TILE_MAX 0xFFFFFC00
+#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
+#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
+#define C_028060_SLICE_TILE_MAX 0xC00003FF
+#define R_028064_CB_COLOR1_SIZE 0x028064
+#define R_028068_CB_COLOR2_SIZE 0x028068
+#define R_02806C_CB_COLOR3_SIZE 0x02806C
+#define R_028070_CB_COLOR4_SIZE 0x028070
+#define R_028074_CB_COLOR5_SIZE 0x028074
+#define R_028078_CB_COLOR6_SIZE 0x028078
+#define R_02807C_CB_COLOR7_SIZE 0x02807C
+#define R_028040_CB_COLOR0_BASE 0x028040
+#define R_028044_CB_COLOR1_BASE 0x028044
+#define R_028048_CB_COLOR2_BASE 0x028048
+#define R_02804C_CB_COLOR3_BASE 0x02804C
+#define R_028050_CB_COLOR4_BASE 0x028050
+#define R_028054_CB_COLOR5_BASE 0x028054
+#define R_028058_CB_COLOR6_BASE 0x028058
+#define R_02805C_CB_COLOR7_BASE 0x02805C
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240
+#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0)
+#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028240_TL_X 0xFFFFC000
+#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028240_TL_Y 0xC000FFFF
+#define R_028C04_PA_SC_AA_CONFIG 0x028C04
+#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
+#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
+#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
+#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
+#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
+#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
+#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
+#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
+#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
+#define R_0288CC_SQ_PGM_CF_OFFSET_PS 0x0288CC
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC
+#define R_0288D0_SQ_PGM_CF_OFFSET_VS 0x0288D0
+#define R_028840_SQ_PGM_START_PS 0x028840
+#define R_028894_SQ_PGM_START_FS 0x028894
+#define R_028858_SQ_PGM_START_VS 0x028858
+#define R_028080_CB_COLOR0_VIEW 0x028080
+#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
+#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
+#define C_028080_SLICE_START 0xFFFFF800
+#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
+#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
+#define C_028080_SLICE_MAX 0xFF001FFF
+#define R_028084_CB_COLOR1_VIEW 0x028084
+#define R_028088_CB_COLOR2_VIEW 0x028088
+#define R_02808C_CB_COLOR3_VIEW 0x02808C
+#define R_028090_CB_COLOR4_VIEW 0x028090
+#define R_028094_CB_COLOR5_VIEW 0x028094
+#define R_028098_CB_COLOR6_VIEW 0x028098
+#define R_02809C_CB_COLOR7_VIEW 0x02809C
+#define R_028100_CB_COLOR0_MASK 0x028100
+#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
+#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
+#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
+#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
+#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
+#define C_028100_FMASK_TILE_MAX 0x00000FFF
+#define R_028104_CB_COLOR1_MASK 0x028104
+#define R_028108_CB_COLOR2_MASK 0x028108
+#define R_02810C_CB_COLOR3_MASK 0x02810C
+#define R_028110_CB_COLOR4_MASK 0x028110
+#define R_028114_CB_COLOR5_MASK 0x028114
+#define R_028118_CB_COLOR6_MASK 0x028118
+#define R_02811C_CB_COLOR7_MASK 0x02811C
+#define R_028040_CB_COLOR0_BASE 0x028040
+#define S_028040_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028040_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028040_BASE_256B 0x00000000
+#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
+#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0280E0_BASE_256B 0x00000000
+#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
+#define R_0280C0_CB_COLOR0_TILE 0x0280C0
+#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0280C0_BASE_256B 0x00000000
+#define R_0280C4_CB_COLOR1_TILE 0x0280C4
+#define R_0280C8_CB_COLOR2_TILE 0x0280C8
+#define R_0280CC_CB_COLOR3_TILE 0x0280CC
+#define R_0280D0_CB_COLOR4_TILE 0x0280D0
+#define R_0280D4_CB_COLOR5_TILE 0x0280D4
+#define R_0280D8_CB_COLOR6_TILE 0x0280D8
+#define R_0280DC_CB_COLOR7_TILE 0x0280DC
+#define R_028808_CB_COLOR_CONTROL 0x028808
+#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0)
+#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1)
+#define C_028808_FOG_ENABLE 0xFFFFFFFE
+#define S_028808_MULTIWRITE_ENABLE(x) (((x) & 0x1) << 1)
+#define G_028808_MULTIWRITE_ENABLE(x) (((x) >> 1) & 0x1)
+#define C_028808_MULTIWRITE_ENABLE 0xFFFFFFFD
+#define S_028808_DITHER_ENABLE(x) (((x) & 0x1) << 2)
+#define G_028808_DITHER_ENABLE(x) (((x) >> 2) & 0x1)
+#define C_028808_DITHER_ENABLE 0xFFFFFFFB
+#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3)
+#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1)
+#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7
+#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
+#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
+#define C_028808_SPECIAL_OP 0xFFFFFF8F
+#define S_028808_PER_MRT_BLEND(x) (((x) & 0x1) << 7)
+#define G_028808_PER_MRT_BLEND(x) (((x) >> 7) & 0x1)
+#define C_028808_PER_MRT_BLEND 0xFFFFFF7F
+#define S_028808_TARGET_BLEND_ENABLE(x) (((x) & 0xFF) << 8)
+#define G_028808_TARGET_BLEND_ENABLE(x) (((x) >> 8) & 0xFF)
+#define C_028808_TARGET_BLEND_ENABLE 0xFFFF00FF
+#define S_028808_ROP3(x) (((x) & 0xFF) << 16)
+#define G_028808_ROP3(x) (((x) >> 16) & 0xFF)
+#define C_028808_ROP3 0xFF00FFFF
+#define R_028614_SPI_VS_OUT_ID_0 0x028614
+#define S_028614_SEMANTIC_0(x) (((x) & 0xFF) << 0)
+#define G_028614_SEMANTIC_0(x) (((x) >> 0) & 0xFF)
+#define C_028614_SEMANTIC_0 0xFFFFFF00
+#define S_028614_SEMANTIC_1(x) (((x) & 0xFF) << 8)
+#define G_028614_SEMANTIC_1(x) (((x) >> 8) & 0xFF)
+#define C_028614_SEMANTIC_1 0xFFFF00FF
+#define S_028614_SEMANTIC_2(x) (((x) & 0xFF) << 16)
+#define G_028614_SEMANTIC_2(x) (((x) >> 16) & 0xFF)
+#define C_028614_SEMANTIC_2 0xFF00FFFF
+#define S_028614_SEMANTIC_3(x) (((x) & 0xFF) << 24)
+#define G_028614_SEMANTIC_3(x) (((x) >> 24) & 0xFF)
+#define C_028614_SEMANTIC_3 0x00FFFFFF
+#define R_028618_SPI_VS_OUT_ID_1 0x028618
+#define R_02861C_SPI_VS_OUT_ID_2 0x02861C
+#define R_028620_SPI_VS_OUT_ID_3 0x028620
+#define R_028624_SPI_VS_OUT_ID_4 0x028624
+#define R_028628_SPI_VS_OUT_ID_5 0x028628
+#define R_02862C_SPI_VS_OUT_ID_6 0x02862C
+#define R_028630_SPI_VS_OUT_ID_7 0x028630
+#define R_028634_SPI_VS_OUT_ID_8 0x028634
+#define R_028638_SPI_VS_OUT_ID_9 0x028638
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
+#define S_038000_DIM(x) (((x) & 0x7) << 0)
+#define G_038000_DIM(x) (((x) >> 0) & 0x7)
+#define C_038000_DIM 0xFFFFFFF8
+#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
+#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
+#define C_038000_TILE_MODE 0xFFFFFF87
+#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
+#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
+#define C_038000_TILE_TYPE 0xFFFFFF7F
+#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
+#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
+#define C_038000_PITCH 0xFFF800FF
+#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
+#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
+#define C_038000_TEX_WIDTH 0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
+#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
+#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
+#define C_038004_TEX_HEIGHT 0xFFFFE000
+#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
+#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
+#define C_038004_TEX_DEPTH 0xFC001FFF
+#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
+#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
+#define C_038004_DATA_FORMAT 0x03FFFFFF
+#define V_038004_COLOR_INVALID 0x00000000
+#define V_038004_COLOR_8 0x00000001
+#define V_038004_COLOR_4_4 0x00000002
+#define V_038004_COLOR_3_3_2 0x00000003
+#define V_038004_COLOR_16 0x00000005
+#define V_038004_COLOR_16_FLOAT 0x00000006
+#define V_038004_COLOR_8_8 0x00000007
+#define V_038004_COLOR_5_6_5 0x00000008
+#define V_038004_COLOR_6_5_5 0x00000009
+#define V_038004_COLOR_1_5_5_5 0x0000000A
+#define V_038004_COLOR_4_4_4_4 0x0000000B
+#define V_038004_COLOR_5_5_5_1 0x0000000C
+#define V_038004_COLOR_32 0x0000000D
+#define V_038004_COLOR_32_FLOAT 0x0000000E
+#define V_038004_COLOR_16_16 0x0000000F
+#define V_038004_COLOR_16_16_FLOAT 0x00000010
+#define V_038004_COLOR_8_24 0x00000011
+#define V_038004_COLOR_8_24_FLOAT 0x00000012
+#define V_038004_COLOR_24_8 0x00000013
+#define V_038004_COLOR_24_8_FLOAT 0x00000014
+#define V_038004_COLOR_10_11_11 0x00000015
+#define V_038004_COLOR_10_11_11_FLOAT 0x00000016
+#define V_038004_COLOR_11_11_10 0x00000017
+#define V_038004_COLOR_11_11_10_FLOAT 0x00000018
+#define V_038004_COLOR_2_10_10_10 0x00000019
+#define V_038004_COLOR_8_8_8_8 0x0000001A
+#define V_038004_COLOR_10_10_10_2 0x0000001B
+#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
+#define V_038004_COLOR_32_32 0x0000001D
+#define V_038004_COLOR_32_32_FLOAT 0x0000001E
+#define V_038004_COLOR_16_16_16_16 0x0000001F
+#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
+#define V_038004_COLOR_32_32_32_32 0x00000022
+#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0 0x038008
+#define S_038008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_038008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_038008_BASE_ADDRESS 0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0 0x03800C
+#define S_03800C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_03800C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_03800C_MIP_ADDRESS 0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
+#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
+#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
+#define C_038010_FORMAT_COMP_X 0xFFFFFFFC
+#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
+#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
+#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
+#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
+#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
+#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
+#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
+#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
+#define C_038010_FORMAT_COMP_W 0xFFFFFF3F
+#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
+#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
+#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
+#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
+#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
+#define C_038010_SRF_MODE_ALL 0xFFFFFBFF
+#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
+#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
+#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
+#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
+#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
+#define C_038010_ENDIAN_SWAP 0xFFFFCFFF
+#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
+#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
+#define C_038010_REQUEST_SIZE 0xFFFF3FFF
+#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
+#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
+#define C_038010_DST_SEL_X 0xFFF8FFFF
+#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
+#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
+#define C_038010_DST_SEL_Y 0xFFC7FFFF
+#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
+#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
+#define C_038010_DST_SEL_Z 0xFE3FFFFF
+#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
+#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
+#define C_038010_DST_SEL_W 0xF1FFFFFF
+#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
+#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
+#define C_038010_BASE_LEVEL 0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
+#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
+#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
+#define C_038014_LAST_LEVEL 0xFFFFFFF0
+#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
+#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
+#define C_038014_BASE_ARRAY 0xFFFE000F
+#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
+#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
+#define C_038014_LAST_ARRAY 0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0 0x038018
+#define S_038018_MPEG_CLAMP(x) (((x) & 0x3) << 0)
+#define G_038018_MPEG_CLAMP(x) (((x) >> 0) & 0x3)
+#define C_038018_MPEG_CLAMP 0xFFFFFFFC
+#define S_038018_PERF_MODULATION(x) (((x) & 0x7) << 5)
+#define G_038018_PERF_MODULATION(x) (((x) >> 5) & 0x7)
+#define C_038018_PERF_MODULATION 0xFFFFFF1F
+#define S_038018_INTERLACED(x) (((x) & 0x1) << 8)
+#define G_038018_INTERLACED(x) (((x) >> 8) & 0x1)
+#define C_038018_INTERLACED 0xFFFFFEFF
+#define S_038018_TYPE(x) (((x) & 0x3) << 30)
+#define G_038018_TYPE(x) (((x) >> 30) & 0x3)
+#define C_038018_TYPE 0x3FFFFFFF
+#define R_008040_WAIT_UNTIL 0x008040
+#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8)
+#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1)
+#define C_008040_WAIT_CP_DMA_IDLE 0xFFFFFEFF
+#define S_008040_WAIT_CMDFIFO(x) (((x) & 0x1) << 10)
+#define G_008040_WAIT_CMDFIFO(x) (((x) >> 10) & 0x1)
+#define C_008040_WAIT_CMDFIFO 0xFFFFFBFF
+#define S_008040_WAIT_2D_IDLE(x) (((x) & 0x1) << 14)
+#define G_008040_WAIT_2D_IDLE(x) (((x) >> 14) & 0x1)
+#define C_008040_WAIT_2D_IDLE 0xFFFFBFFF
+#define S_008040_WAIT_3D_IDLE(x) (((x) & 0x1) << 15)
+#define G_008040_WAIT_3D_IDLE(x) (((x) >> 15) & 0x1)
+#define C_008040_WAIT_3D_IDLE 0xFFFF7FFF
+#define S_008040_WAIT_2D_IDLECLEAN(x) (((x) & 0x1) << 16)
+#define G_008040_WAIT_2D_IDLECLEAN(x) (((x) >> 16) & 0x1)
+#define C_008040_WAIT_2D_IDLECLEAN 0xFFFEFFFF
+#define S_008040_WAIT_3D_IDLECLEAN(x) (((x) & 0x1) << 17)
+#define G_008040_WAIT_3D_IDLECLEAN(x) (((x) >> 17) & 0x1)
+#define C_008040_WAIT_3D_IDLECLEAN 0xFFFDFFFF
+#define S_008040_WAIT_EXTERN_SIG(x) (((x) & 0x1) << 19)
+#define G_008040_WAIT_EXTERN_SIG(x) (((x) >> 19) & 0x1)
+#define C_008040_WAIT_EXTERN_SIG 0xFFF7FFFF
+#define S_008040_CMDFIFO_ENTRIES(x) (((x) & 0x1F) << 20)
+#define G_008040_CMDFIFO_ENTRIES(x) (((x) >> 20) & 0x1F)
+#define C_008040_CMDFIFO_ENTRIES 0xFE0FFFFF
+#define R_008958_VGT_PRIMITIVE_TYPE 0x008958
+#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0)
+#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
+#define C_008958_PRIM_TYPE 0xFFFFFFC0
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2 0x008C08
+#define S_008C08_NUM_GS_GPRS(x) (((x) & 0xFF) << 0)
+#define G_008C08_NUM_GS_GPRS(x) (((x) >> 0) & 0xFF)
+#define C_008C08_NUM_GS_GPRS 0xFFFFFF00
+#define S_008C08_NUM_ES_GPRS(x) (((x) & 0xFF) << 16)
+#define G_008C08_NUM_ES_GPRS(x) (((x) >> 16) & 0xFF)
+#define C_008C08_NUM_ES_GPRS 0xFF00FFFF
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x008D8C
+#define S_008D8C_RING0_OFFSET(x) (((x) & 0xFF) << 0)
+#define G_008D8C_RING0_OFFSET(x) (((x) >> 0) & 0xFF)
+#define C_008D8C_RING0_OFFSET 0xFFFFFF00
+#define S_008D8C_ISOLATE_ES_ENABLE(x) (((x) & 0x1) << 12)
+#define G_008D8C_ISOLATE_ES_ENABLE(x) (((x) >> 12) & 0x1)
+#define C_008D8C_ISOLATE_ES_ENABLE 0xFFFFEFFF
+#define S_008D8C_ISOLATE_GS_ENABLE(x) (((x) & 0x1) << 13)
+#define G_008D8C_ISOLATE_GS_ENABLE(x) (((x) >> 13) & 0x1)
+#define C_008D8C_ISOLATE_GS_ENABLE 0xFFFFDFFF
+#define S_008D8C_VS_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 14)
+#define G_008D8C_VS_PC_LIMIT_ENABLE(x) (((x) >> 14) & 0x1)
+#define C_008D8C_VS_PC_LIMIT_ENABLE 0xFFFFBFFF
+#define R_009508_TA_CNTL_AUX 0x009508
+#define S_009508_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 0)
+#define G_009508_DISABLE_CUBE_WRAP(x) (((x) >> 0) & 0x1)
+#define C_009508_DISABLE_CUBE_WRAP 0xFFFFFFFE
+#define S_009508_SYNC_GRADIENT(x) (((x) & 0x1) << 24)
+#define G_009508_SYNC_GRADIENT(x) (((x) >> 24) & 0x1)
+#define C_009508_SYNC_GRADIENT 0xFEFFFFFF
+#define S_009508_SYNC_WALKER(x) (((x) & 0x1) << 25)
+#define G_009508_SYNC_WALKER(x) (((x) >> 25) & 0x1)
+#define C_009508_SYNC_WALKER 0xFDFFFFFF
+#define S_009508_SYNC_ALIGNER(x) (((x) & 0x1) << 26)
+#define G_009508_SYNC_ALIGNER(x) (((x) >> 26) & 0x1)
+#define C_009508_SYNC_ALIGNER 0xFBFFFFFF
+#define S_009508_BILINEAR_PRECISION(x) (((x) & 0x1) << 31)
+#define G_009508_BILINEAR_PRECISION(x) (((x) >> 31) & 0x1)
+#define C_009508_BILINEAR_PRECISION 0x7FFFFFFF
+#define R_009714_VC_ENHANCE 0x009714
+#define R_009830_DB_DEBUG 0x009830
+#define R_009838_DB_WATERMARKS 0x009838
+#define S_009838_DEPTH_FREE(x) (((x) & 0x1F) << 0)
+#define G_009838_DEPTH_FREE(x) (((x) >> 0) & 0x1F)
+#define C_009838_DEPTH_FREE 0xFFFFFFE0
+#define S_009838_DEPTH_FLUSH(x) (((x) & 0x3F) << 5)
+#define G_009838_DEPTH_FLUSH(x) (((x) >> 5) & 0x3F)
+#define C_009838_DEPTH_FLUSH 0xFFFFF81F
+#define S_009838_FORCE_SUMMARIZE(x) (((x) & 0xF) << 11)
+#define G_009838_FORCE_SUMMARIZE(x) (((x) >> 11) & 0xF)
+#define C_009838_FORCE_SUMMARIZE 0xFFFF87FF
+#define S_009838_DEPTH_PENDING_FREE(x) (((x) & 0x1F) << 15)
+#define G_009838_DEPTH_PENDING_FREE(x) (((x) >> 15) & 0x1F)
+#define C_009838_DEPTH_PENDING_FREE 0xFFF07FFF
+#define S_009838_DEPTH_CACHELINE_FREE(x) (((x) & 0x1F) << 20)
+#define G_009838_DEPTH_CACHELINE_FREE(x) (((x) >> 20) & 0x1F)
+#define C_009838_DEPTH_CACHELINE_FREE 0xFE0FFFFF
+#define S_009838_EARLY_Z_PANIC_DISABLE(x) (((x) & 0x1) << 25)
+#define G_009838_EARLY_Z_PANIC_DISABLE(x) (((x) >> 25) & 0x1)
+#define C_009838_EARLY_Z_PANIC_DISABLE 0xFDFFFFFF
+#define S_009838_LATE_Z_PANIC_DISABLE(x) (((x) & 0x1) << 26)
+#define G_009838_LATE_Z_PANIC_DISABLE(x) (((x) >> 26) & 0x1)
+#define C_009838_LATE_Z_PANIC_DISABLE 0xFBFFFFFF
+#define S_009838_RE_Z_PANIC_DISABLE(x) (((x) & 0x1) << 27)
+#define G_009838_RE_Z_PANIC_DISABLE(x) (((x) >> 27) & 0x1)
+#define C_009838_RE_Z_PANIC_DISABLE 0xF7FFFFFF
+#define S_009838_DB_EXTRA_DEBUG(x) (((x) & 0xF) << 28)
+#define G_009838_DB_EXTRA_DEBUG(x) (((x) >> 28) & 0xF)
+#define C_009838_DB_EXTRA_DEBUG 0x0FFFFFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030
+#define S_028030_TL_X(x) (((x) & 0x7FFF) << 0)
+#define G_028030_TL_X(x) (((x) >> 0) & 0x7FFF)
+#define C_028030_TL_X 0xFFFF8000
+#define S_028030_TL_Y(x) (((x) & 0x7FFF) << 16)
+#define G_028030_TL_Y(x) (((x) >> 16) & 0x7FFF)
+#define C_028030_TL_Y 0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034
+#define S_028034_BR_X(x) (((x) & 0x7FFF) << 0)
+#define G_028034_BR_X(x) (((x) >> 0) & 0x7FFF)
+#define C_028034_BR_X 0xFFFF8000
+#define S_028034_BR_Y(x) (((x) & 0x7FFF) << 16)
+#define G_028034_BR_Y(x) (((x) >> 16) & 0x7FFF)
+#define C_028034_BR_Y 0x8000FFFF
+#define R_028200_PA_SC_WINDOW_OFFSET 0x028200
+#define S_028200_WINDOW_X_OFFSET(x) (((x) & 0x7FFF) << 0)
+#define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0x7FFF)
+#define C_028200_WINDOW_X_OFFSET 0xFFFF8000
+#define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0x7FFF) << 16)
+#define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0x7FFF)
+#define C_028200_WINDOW_Y_OFFSET 0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204
+#define S_028204_TL_X(x) (((x) & 0x3FFF) << 0)
+#define G_028204_TL_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028204_TL_X 0xFFFFC000
+#define S_028204_TL_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028204_TL_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028204_TL_Y 0xC000FFFF
+#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
+#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
+#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208
+#define S_028208_BR_X(x) (((x) & 0x3FFF) << 0)
+#define G_028208_BR_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028208_BR_X 0xFFFFC000
+#define S_028208_BR_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028208_BR_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028208_BR_Y 0xC000FFFF
+#define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C
+#define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0)
+#define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF)
+#define C_02820C_CLIP_RULE 0xFFFF0000
+#define R_028210_PA_SC_CLIPRECT_0_TL 0x028210
+#define S_028210_TL_X(x) (((x) & 0x3FFF) << 0)
+#define G_028210_TL_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028210_TL_X 0xFFFFC000
+#define S_028210_TL_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028210_TL_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028210_TL_Y 0xC000FFFF
+#define R_028214_PA_SC_CLIPRECT_0_BR 0x028214
+#define S_028214_BR_X(x) (((x) & 0x3FFF) << 0)
+#define G_028214_BR_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028214_BR_X 0xFFFFC000
+#define S_028214_BR_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028214_BR_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028214_BR_Y 0xC000FFFF
+#define R_028218_PA_SC_CLIPRECT_1_TL 0x028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C
+#define R_028220_PA_SC_CLIPRECT_2_TL 0x028220
+#define R_028224_PA_SC_CLIPRECT_2_BR 0x028224
+#define R_028228_PA_SC_CLIPRECT_3_TL 0x028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C
+#define R_028230_PA_SC_EDGERULE 0x028230
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240
+#define S_028240_TL_X(x) (((x) & 0x3FFF) << 0)
+#define G_028240_TL_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028240_TL_X 0xFFFFC000
+#define S_028240_TL_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028240_TL_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028240_TL_Y 0xC000FFFF
+#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
+#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
+#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244
+#define S_028244_BR_X(x) (((x) & 0x3FFF) << 0)
+#define G_028244_BR_X(x) (((x) >> 0) & 0x3FFF)
+#define C_028244_BR_X 0xFFFFC000
+#define S_028244_BR_Y(x) (((x) & 0x3FFF) << 16)
+#define G_028244_BR_Y(x) (((x) >> 16) & 0x3FFF)
+#define C_028244_BR_Y 0xC000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
+#define S_0282D0_VPORT_ZMIN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0282D0_VPORT_ZMIN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0282D0_VPORT_ZMIN 0x00000000
+#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
+#define S_0282D4_VPORT_ZMAX(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0282D4_VPORT_ZMAX(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0282D4_VPORT_ZMAX 0x00000000
+#define R_028350_SX_MISC 0x028350
+#define S_028350_MULTIPASS(x) (((x) & 0x1) << 0)
+#define G_028350_MULTIPASS(x) (((x) >> 0) & 0x1)
+#define C_028350_MULTIPASS 0xFFFFFFFE
+#define R_028380_SQ_VTX_SEMANTIC_0 0x028380
+#define S_028380_SEMANTIC_ID(x) (((x) & 0xFF) << 0)
+#define G_028380_SEMANTIC_ID(x) (((x) >> 0) & 0xFF)
+#define C_028380_SEMANTIC_ID 0xFFFFFF00
+#define R_028384_SQ_VTX_SEMANTIC_1 0x028384
+#define R_028388_SQ_VTX_SEMANTIC_2 0x028388
+#define R_02838C_SQ_VTX_SEMANTIC_3 0x02838C
+#define R_028390_SQ_VTX_SEMANTIC_4 0x028390
+#define R_028394_SQ_VTX_SEMANTIC_5 0x028394
+#define R_028398_SQ_VTX_SEMANTIC_6 0x028398
+#define R_02839C_SQ_VTX_SEMANTIC_7 0x02839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8 0x0283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9 0x0283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10 0x0283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11 0x0283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12 0x0283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13 0x0283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14 0x0283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15 0x0283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16 0x0283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17 0x0283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18 0x0283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19 0x0283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20 0x0283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21 0x0283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22 0x0283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23 0x0283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24 0x0283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25 0x0283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26 0x0283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27 0x0283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28 0x0283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29 0x0283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30 0x0283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31 0x0283FC
+#define R_028400_VGT_MAX_VTX_INDX 0x028400
+#define S_028400_MAX_INDX(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028400_MAX_INDX(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028400_MAX_INDX 0x00000000
+#define R_028404_VGT_MIN_VTX_INDX 0x028404
+#define S_028404_MIN_INDX(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028404_MIN_INDX(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028404_MIN_INDX 0x00000000
+#define R_028408_VGT_INDX_OFFSET 0x028408
+#define S_028408_INDX_OFFSET(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028408_INDX_OFFSET(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028408_INDX_OFFSET 0x00000000
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C
+#define S_02840C_RESET_INDX(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_02840C_RESET_INDX(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_02840C_RESET_INDX 0x00000000
+#define R_028410_SX_ALPHA_TEST_CONTROL 0x028410
+#define S_028410_ALPHA_FUNC(x) (((x) & 0x7) << 0)
+#define G_028410_ALPHA_FUNC(x) (((x) >> 0) & 0x7)
+#define C_028410_ALPHA_FUNC 0xFFFFFFF8
+#define S_028410_ALPHA_TEST_ENABLE(x) (((x) & 0x1) << 3)
+#define G_028410_ALPHA_TEST_ENABLE(x) (((x) >> 3) & 0x1)
+#define C_028410_ALPHA_TEST_ENABLE 0xFFFFFFF7
+#define S_028410_ALPHA_TEST_BYPASS(x) (((x) & 0x1) << 8)
+#define G_028410_ALPHA_TEST_BYPASS(x) (((x) >> 8) & 0x1)
+#define C_028410_ALPHA_TEST_BYPASS 0xFFFFFEFF
+#define R_028414_CB_BLEND_RED 0x028414
+#define S_028414_BLEND_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028414_BLEND_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028414_BLEND_RED 0x00000000
+#define R_028418_CB_BLEND_GREEN 0x028418
+#define S_028418_BLEND_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028418_BLEND_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028418_BLEND_GREEN 0x00000000
+#define R_02841C_CB_BLEND_BLUE 0x02841C
+#define S_02841C_BLEND_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_02841C_BLEND_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_02841C_BLEND_BLUE 0x00000000
+#define R_028420_CB_BLEND_ALPHA 0x028420
+#define S_028420_BLEND_ALPHA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028420_BLEND_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028420_BLEND_ALPHA 0x00000000
+#define R_028438_SX_ALPHA_REF 0x028438
+#define S_028438_ALPHA_REF(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028438_ALPHA_REF(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028438_ALPHA_REF 0x00000000
+#define R_0286C8_SPI_THREAD_GROUPING 0x0286C8
+#define S_0286C8_PS_GROUPING(x) (((x) & 0x1F) << 0)
+#define G_0286C8_PS_GROUPING(x) (((x) >> 0) & 0x1F)
+#define C_0286C8_PS_GROUPING 0xFFFFFFE0
+#define S_0286C8_VS_GROUPING(x) (((x) & 0x1F) << 8)
+#define G_0286C8_VS_GROUPING(x) (((x) >> 8) & 0x1F)
+#define C_0286C8_VS_GROUPING 0xFFFFE0FF
+#define S_0286C8_GS_GROUPING(x) (((x) & 0x1F) << 16)
+#define G_0286C8_GS_GROUPING(x) (((x) >> 16) & 0x1F)
+#define C_0286C8_GS_GROUPING 0xFFE0FFFF
+#define S_0286C8_ES_GROUPING(x) (((x) & 0x1F) << 24)
+#define G_0286C8_ES_GROUPING(x) (((x) >> 24) & 0x1F)
+#define C_0286C8_ES_GROUPING 0xE0FFFFFF
+#define R_0286D8_SPI_INPUT_Z 0x0286D8
+#define S_0286D8_PROVIDE_Z_TO_SPI(x) (((x) & 0x1) << 0)
+#define G_0286D8_PROVIDE_Z_TO_SPI(x) (((x) >> 0) & 0x1)
+#define C_0286D8_PROVIDE_Z_TO_SPI 0xFFFFFFFE
+#define R_0286DC_SPI_FOG_CNTL 0x0286DC
+#define S_0286DC_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 0)
+#define G_0286DC_PASS_FOG_THROUGH_PS(x) (((x) >> 0) & 0x1)
+#define C_0286DC_PASS_FOG_THROUGH_PS 0xFFFFFFFE
+#define S_0286DC_PIXEL_FOG_FUNC(x) (((x) & 0x3) << 1)
+#define G_0286DC_PIXEL_FOG_FUNC(x) (((x) >> 1) & 0x3)
+#define C_0286DC_PIXEL_FOG_FUNC 0xFFFFFFF9
+#define S_0286DC_PIXEL_FOG_SRC_SEL(x) (((x) & 0x1) << 3)
+#define G_0286DC_PIXEL_FOG_SRC_SEL(x) (((x) >> 3) & 0x1)
+#define C_0286DC_PIXEL_FOG_SRC_SEL 0xFFFFFFF7
+#define S_0286DC_VS_FOG_CLAMP_DISABLE(x) (((x) & 0x1) << 4)
+#define G_0286DC_VS_FOG_CLAMP_DISABLE(x) (((x) >> 4) & 0x1)
+#define C_0286DC_VS_FOG_CLAMP_DISABLE 0xFFFFFFEF
+#define R_0286E0_SPI_FOG_FUNC_SCALE 0x0286E0
+#define S_0286E0_VALUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0286E0_VALUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0286E0_VALUE 0x00000000
+#define R_0286E4_SPI_FOG_FUNC_BIAS 0x0286E4
+#define S_0286E4_VALUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_0286E4_VALUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_0286E4_VALUE 0x00000000
+#define R_0287A0_CB_SHADER_CONTROL 0x0287A0
+#define S_0287A0_RT0_ENABLE(x) (((x) & 0x1) << 0)
+#define G_0287A0_RT0_ENABLE(x) (((x) >> 0) & 0x1)
+#define C_0287A0_RT0_ENABLE 0xFFFFFFFE
+#define S_0287A0_RT1_ENABLE(x) (((x) & 0x1) << 1)
+#define G_0287A0_RT1_ENABLE(x) (((x) >> 1) & 0x1)
+#define C_0287A0_RT1_ENABLE 0xFFFFFFFD
+#define S_0287A0_RT2_ENABLE(x) (((x) & 0x1) << 2)
+#define G_0287A0_RT2_ENABLE(x) (((x) >> 2) & 0x1)
+#define C_0287A0_RT2_ENABLE 0xFFFFFFFB
+#define S_0287A0_RT3_ENABLE(x) (((x) & 0x1) << 3)
+#define G_0287A0_RT3_ENABLE(x) (((x) >> 3) & 0x1)
+#define C_0287A0_RT3_ENABLE 0xFFFFFFF7
+#define S_0287A0_RT4_ENABLE(x) (((x) & 0x1) << 4)
+#define G_0287A0_RT4_ENABLE(x) (((x) >> 4) & 0x1)
+#define C_0287A0_RT4_ENABLE 0xFFFFFFEF
+#define S_0287A0_RT5_ENABLE(x) (((x) & 0x1) << 5)
+#define G_0287A0_RT5_ENABLE(x) (((x) >> 5) & 0x1)
+#define C_0287A0_RT5_ENABLE 0xFFFFFFDF
+#define S_0287A0_RT6_ENABLE(x) (((x) & 0x1) << 6)
+#define G_0287A0_RT6_ENABLE(x) (((x) >> 6) & 0x1)
+#define C_0287A0_RT6_ENABLE 0xFFFFFFBF
+#define S_0287A0_RT7_ENABLE(x) (((x) & 0x1) << 7)
+#define G_0287A0_RT7_ENABLE(x) (((x) >> 7) & 0x1)
+#define C_0287A0_RT7_ENABLE 0xFFFFFF7F
+#define R_028894_SQ_PGM_START_FS 0x028894
+#define S_028894_PGM_START(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028894_PGM_START(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028894_PGM_START 0x00000000
+#define R_0288A4_SQ_PGM_RESOURCES_FS 0x0288A4
+#define S_0288A4_NUM_GPRS(x) (((x) & 0xFF) << 0)
+#define G_0288A4_NUM_GPRS(x) (((x) >> 0) & 0xFF)
+#define C_0288A4_NUM_GPRS 0xFFFFFF00
+#define S_0288A4_STACK_SIZE(x) (((x) & 0xFF) << 8)
+#define G_0288A4_STACK_SIZE(x) (((x) >> 8) & 0xFF)
+#define C_0288A4_STACK_SIZE 0xFFFF00FF
+#define S_0288A4_DX10_CLAMP(x) (((x) & 0x1) << 21)
+#define G_0288A4_DX10_CLAMP(x) (((x) >> 21) & 0x1)
+#define C_0288A4_DX10_CLAMP 0xFFDFFFFF
+#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
+#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288A8_ITEMSIZE 0xFFFF8000
+#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
+#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288AC_ITEMSIZE 0xFFFF8000
+#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
+#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288B0_ITEMSIZE 0xFFFF8000
+#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
+#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288B4_ITEMSIZE 0xFFFF8000
+#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
+#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288B8_ITEMSIZE 0xFFFF8000
+#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
+#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288BC_ITEMSIZE 0xFFFF8000
+#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
+#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288C0_ITEMSIZE 0xFFFF8000
+#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
+#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288C4_ITEMSIZE 0xFFFF8000
+#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
+#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
+#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
+#define C_0288C8_ITEMSIZE 0xFFFF8000
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS 0x0288DC
+#define S_0288DC_PGM_CF_OFFSET(x) (((x) & 0xFFFFF) << 0)
+#define G_0288DC_PGM_CF_OFFSET(x) (((x) >> 0) & 0xFFFFF)
+#define C_0288DC_PGM_CF_OFFSET 0xFFF00000
+#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10
+#define S_028A10_PATH_SELECT(x) (((x) & 0x3) << 0)
+#define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x3)
+#define C_028A10_PATH_SELECT 0xFFFFFFFC
+#define R_028A14_VGT_HOS_CNTL 0x028A14
+#define S_028A14_TESS_MODE(x) (((x) & 0x3) << 0)
+#define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x3)
+#define C_028A14_TESS_MODE 0xFFFFFFFC
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18
+#define S_028A18_MAX_TESS(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028A18_MAX_TESS(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028A18_MAX_TESS 0x00000000
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C
+#define S_028A1C_MIN_TESS(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028A1C_MIN_TESS(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028A1C_MIN_TESS 0x00000000
+#define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20
+#define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
+#define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
+#define C_028A20_REUSE_DEPTH 0xFFFFFF00
+#define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24
+#define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0)
+#define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F)
+#define C_028A24_PRIM_TYPE 0xFFFFFFE0
+#define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14)
+#define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1)
+#define C_028A24_RETAIN_ORDER 0xFFFFBFFF
+#define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15)
+#define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1)
+#define C_028A24_RETAIN_QUADS 0xFFFF7FFF
+#define S_028A24_PRIM_ORDER(x) (((x) & 0x7) << 16)
+#define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x7)
+#define C_028A24_PRIM_ORDER 0xFFF8FFFF
+#define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28
+#define S_028A28_FIRST_DECR(x) (((x) & 0xF) << 0)
+#define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0xF)
+#define C_028A28_FIRST_DECR 0xFFFFFFF0
+#define R_028A2C_VGT_GROUP_DECR 0x028A2C
+#define S_028A2C_DECR(x) (((x) & 0xF) << 0)
+#define G_028A2C_DECR(x) (((x) >> 0) & 0xF)
+#define C_028A2C_DECR 0xFFFFFFF0
+#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30
+#define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0)
+#define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1)
+#define C_028A30_COMP_X_EN 0xFFFFFFFE
+#define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1)
+#define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1)
+#define C_028A30_COMP_Y_EN 0xFFFFFFFD
+#define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2)
+#define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1)
+#define C_028A30_COMP_Z_EN 0xFFFFFFFB
+#define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3)
+#define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1)
+#define C_028A30_COMP_W_EN 0xFFFFFFF7
+#define S_028A30_STRIDE(x) (((x) & 0xFF) << 8)
+#define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF)
+#define C_028A30_STRIDE 0xFFFF00FF
+#define S_028A30_SHIFT(x) (((x) & 0xFF) << 16)
+#define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF)
+#define C_028A30_SHIFT 0xFF00FFFF
+#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34
+#define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0)
+#define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1)
+#define C_028A34_COMP_X_EN 0xFFFFFFFE
+#define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1)
+#define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1)
+#define C_028A34_COMP_Y_EN 0xFFFFFFFD
+#define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2)
+#define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1)
+#define C_028A34_COMP_Z_EN 0xFFFFFFFB
+#define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3)
+#define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1)
+#define C_028A34_COMP_W_EN 0xFFFFFFF7
+#define S_028A34_STRIDE(x) (((x) & 0xFF) << 8)
+#define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF)
+#define C_028A34_STRIDE 0xFFFF00FF
+#define S_028A34_SHIFT(x) (((x) & 0xFF) << 16)
+#define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF)
+#define C_028A34_SHIFT 0xFF00FFFF
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38
+#define S_028A38_X_CONV(x) (((x) & 0xF) << 0)
+#define G_028A38_X_CONV(x) (((x) >> 0) & 0xF)
+#define C_028A38_X_CONV 0xFFFFFFF0
+#define S_028A38_X_OFFSET(x) (((x) & 0xF) << 4)
+#define G_028A38_X_OFFSET(x) (((x) >> 4) & 0xF)
+#define C_028A38_X_OFFSET 0xFFFFFF0F
+#define S_028A38_Y_CONV(x) (((x) & 0xF) << 8)
+#define G_028A38_Y_CONV(x) (((x) >> 8) & 0xF)
+#define C_028A38_Y_CONV 0xFFFFF0FF
+#define S_028A38_Y_OFFSET(x) (((x) & 0xF) << 12)
+#define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0xF)
+#define C_028A38_Y_OFFSET 0xFFFF0FFF
+#define S_028A38_Z_CONV(x) (((x) & 0xF) << 16)
+#define G_028A38_Z_CONV(x) (((x) >> 16) & 0xF)
+#define C_028A38_Z_CONV 0xFFF0FFFF
+#define S_028A38_Z_OFFSET(x) (((x) & 0xF) << 20)
+#define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0xF)
+#define C_028A38_Z_OFFSET 0xFF0FFFFF
+#define S_028A38_W_CONV(x) (((x) & 0xF) << 24)
+#define G_028A38_W_CONV(x) (((x) >> 24) & 0xF)
+#define C_028A38_W_CONV 0xF0FFFFFF
+#define S_028A38_W_OFFSET(x) (((x) & 0xF) << 28)
+#define G_028A38_W_OFFSET(x) (((x) >> 28) & 0xF)
+#define C_028A38_W_OFFSET 0x0FFFFFFF
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C
+#define S_028A3C_X_CONV(x) (((x) & 0xF) << 0)
+#define G_028A3C_X_CONV(x) (((x) >> 0) & 0xF)
+#define C_028A3C_X_CONV 0xFFFFFFF0
+#define S_028A3C_X_OFFSET(x) (((x) & 0xF) << 4)
+#define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0xF)
+#define C_028A3C_X_OFFSET 0xFFFFFF0F
+#define S_028A3C_Y_CONV(x) (((x) & 0xF) << 8)
+#define G_028A3C_Y_CONV(x) (((x) >> 8) & 0xF)
+#define C_028A3C_Y_CONV 0xFFFFF0FF
+#define S_028A3C_Y_OFFSET(x) (((x) & 0xF) << 12)
+#define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0xF)
+#define C_028A3C_Y_OFFSET 0xFFFF0FFF
+#define S_028A3C_Z_CONV(x) (((x) & 0xF) << 16)
+#define G_028A3C_Z_CONV(x) (((x) >> 16) & 0xF)
+#define C_028A3C_Z_CONV 0xFFF0FFFF
+#define S_028A3C_Z_OFFSET(x) (((x) & 0xF) << 20)
+#define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0xF)
+#define C_028A3C_Z_OFFSET 0xFF0FFFFF
+#define S_028A3C_W_CONV(x) (((x) & 0xF) << 24)
+#define G_028A3C_W_CONV(x) (((x) >> 24) & 0xF)
+#define C_028A3C_W_CONV 0xF0FFFFFF
+#define S_028A3C_W_OFFSET(x) (((x) & 0xF) << 28)
+#define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0xF)
+#define C_028A3C_W_OFFSET 0x0FFFFFFF
+#define R_028A40_VGT_GS_MODE 0x028A40
+#define S_028A40_MODE(x) (((x) & 0x3) << 0)
+#define G_028A40_MODE(x) (((x) >> 0) & 0x3)
+#define C_028A40_MODE 0xFFFFFFFC
+#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 2)
+#define G_028A40_ES_PASSTHRU(x) (((x) >> 2) & 0x1)
+#define C_028A40_ES_PASSTHRU 0xFFFFFFFB
+#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3)
+#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3)
+#define C_028A40_CUT_MODE 0xFFFFFFE7
+#define R_028A4C_PA_SC_MODE_CNTL 0x028A4C
+#define S_028A4C_MSAA_ENABLE(x) (((x) & 0x1) << 0)
+#define G_028A4C_MSAA_ENABLE(x) (((x) >> 0) & 0x1)
+#define C_028A4C_MSAA_ENABLE 0xFFFFFFFE
+#define S_028A4C_CLIPRECT_ENABLE(x) (((x) & 0x1) << 1)
+#define G_028A4C_CLIPRECT_ENABLE(x) (((x) >> 1) & 0x1)
+#define C_028A4C_CLIPRECT_ENABLE 0xFFFFFFFD
+#define S_028A4C_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2)
+#define G_028A4C_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1)
+#define C_028A4C_LINE_STIPPLE_ENABLE 0xFFFFFFFB
+#define S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) & 0x1) << 3)
+#define G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) >> 3) & 0x1)
+#define C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB 0xFFFFFFF7
+#define S_028A4C_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 4)
+#define G_028A4C_WALK_ORDER_ENABLE(x) (((x) >> 4) & 0x1)
+#define C_028A4C_WALK_ORDER_ENABLE 0xFFFFFFEF
+#define S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x) (((x) & 0x1) << 5)
+#define G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x) (((x) >> 5) & 0x1)
+#define C_028A4C_HALVE_DETAIL_SAMPLE_PERF 0xFFFFFFDF
+#define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 6)
+#define G_028A4C_WALK_SIZE(x) (((x) >> 6) & 0x1)
+#define C_028A4C_WALK_SIZE 0xFFFFFFBF
+#define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 7)
+#define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 7) & 0x1)
+#define C_028A4C_WALK_ALIGNMENT 0xFFFFFF7F
+#define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 8)
+#define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 8) & 0x1)
+#define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFEFF
+#define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 9)
+#define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 9) & 0x1)
+#define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFDFF
+#define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 10)
+#define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 10) & 0x1)
+#define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFFBFF
+#define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 11)
+#define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 11) & 0x1)
+#define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFFF7FF
+#define S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) & 0x1) << 12)
+#define G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) >> 12) & 0x1)
+#define C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE 0xFFFFEFFF
+#define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 13)
+#define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 13) & 0x1)
+#define C_028A4C_TILE_COVER_DISABLE 0xFFFFDFFF
+#define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 14)
+#define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 14) & 0x1)
+#define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFFFFBFFF
+#define S_028A4C_FORCE_EOV_TILE_ENABLE(x) (((x) & 0x1) << 15)
+#define G_028A4C_FORCE_EOV_TILE_ENABLE(x) (((x) >> 15) & 0x1)
+#define C_028A4C_FORCE_EOV_TILE_ENABLE 0xFFFF7FFF
+#define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 16)
+#define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 16) & 0x1)
+#define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFFFEFFFF
+#define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 17)
+#define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 17) & 0x1)
+#define C_028A4C_PS_ITER_SAMPLE 0xFFFDFFFF
+#define R_028A84_VGT_PRIMITIVEID_EN 0x028A84
+#define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0)
+#define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1)
+#define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE
+#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94
+#define S_028A94_RESET_EN(x) (((x) & 0x1) << 0)
+#define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1)
+#define C_028A94_RESET_EN 0xFFFFFFFE
+#define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0
+#define S_028AA0_STEP_RATE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028AA0_STEP_RATE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028AA0_STEP_RATE 0x00000000
+#define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4
+#define S_028AA4_STEP_RATE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028AA4_STEP_RATE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028AA4_STEP_RATE 0x00000000
+#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
+#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
+#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
+#define C_028AB0_STREAMOUT 0xFFFFFFFE
+#define R_028AB4_VGT_REUSE_OFF 0x028AB4
+#define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0)
+#define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1)
+#define C_028AB4_REUSE_OFF 0xFFFFFFFE
+#define R_028AB8_VGT_VTX_CNT_EN 0x028AB8
+#define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0)
+#define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1)
+#define C_028AB8_VTX_CNT_EN 0xFFFFFFFE
+#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
+#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
+#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
+#define C_028B20_BUFFER_0_EN 0xFFFFFFFE
+#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
+#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
+#define C_028B20_BUFFER_1_EN 0xFFFFFFFD
+#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
+#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
+#define C_028B20_BUFFER_2_EN 0xFFFFFFFB
+#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
+#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
+#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0x028C20
+#define S_028C20_S4_X(x) (((x) & 0xF) << 0)
+#define G_028C20_S4_X(x) (((x) >> 0) & 0xF)
+#define C_028C20_S4_X 0xFFFFFFF0
+#define S_028C20_S4_Y(x) (((x) & 0xF) << 4)
+#define G_028C20_S4_Y(x) (((x) >> 4) & 0xF)
+#define C_028C20_S4_Y 0xFFFFFF0F
+#define S_028C20_S5_X(x) (((x) & 0xF) << 8)
+#define G_028C20_S5_X(x) (((x) >> 8) & 0xF)
+#define C_028C20_S5_X 0xFFFFF0FF
+#define S_028C20_S5_Y(x) (((x) & 0xF) << 12)
+#define G_028C20_S5_Y(x) (((x) >> 12) & 0xF)
+#define C_028C20_S5_Y 0xFFFF0FFF
+#define S_028C20_S6_X(x) (((x) & 0xF) << 16)
+#define G_028C20_S6_X(x) (((x) >> 16) & 0xF)
+#define C_028C20_S6_X 0xFFF0FFFF
+#define S_028C20_S6_Y(x) (((x) & 0xF) << 20)
+#define G_028C20_S6_Y(x) (((x) >> 20) & 0xF)
+#define C_028C20_S6_Y 0xFF0FFFFF
+#define S_028C20_S7_X(x) (((x) & 0xF) << 24)
+#define G_028C20_S7_X(x) (((x) >> 24) & 0xF)
+#define C_028C20_S7_X 0xF0FFFFFF
+#define S_028C20_S7_Y(x) (((x) & 0xF) << 28)
+#define G_028C20_S7_Y(x) (((x) >> 28) & 0xF)
+#define C_028C20_S7_Y 0x0FFFFFFF
+#define R_028C30_CB_CLRCMP_CONTROL 0x028C30
+#define S_028C30_CLRCMP_FCN_SRC(x) (((x) & 0x7) << 0)
+#define G_028C30_CLRCMP_FCN_SRC(x) (((x) >> 0) & 0x7)
+#define C_028C30_CLRCMP_FCN_SRC 0xFFFFFFF8
+#define S_028C30_CLRCMP_FCN_DST(x) (((x) & 0x7) << 8)
+#define G_028C30_CLRCMP_FCN_DST(x) (((x) >> 8) & 0x7)
+#define C_028C30_CLRCMP_FCN_DST 0xFFFFF8FF
+#define S_028C30_CLRCMP_FCN_SEL(x) (((x) & 0x3) << 24)
+#define G_028C30_CLRCMP_FCN_SEL(x) (((x) >> 24) & 0x3)
+#define C_028C30_CLRCMP_FCN_SEL 0xFCFFFFFF
+#define R_028C34_CB_CLRCMP_SRC 0x028C34
+#define S_028C34_CLRCMP_SRC(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028C34_CLRCMP_SRC(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028C34_CLRCMP_SRC 0x00000000
+#define R_028C38_CB_CLRCMP_DST 0x028C38
+#define S_028C38_CLRCMP_DST(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028C38_CLRCMP_DST(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028C38_CLRCMP_DST 0x00000000
+#define R_028C3C_CB_CLRCMP_MSK 0x028C3C
+#define S_028C3C_CLRCMP_MSK(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028C3C_CLRCMP_MSK(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028C3C_CLRCMP_MSK 0x00000000
+#define R_0085F0_CP_COHER_CNTL 0x0085F0
+#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
+#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
+#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
+#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
+#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
+#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
+#define S_0085F0_SO0_DEST_BASE_ENA(x) (((x) & 0x1) << 2)
+#define G_0085F0_SO0_DEST_BASE_ENA(x) (((x) >> 2) & 0x1)
+#define C_0085F0_SO0_DEST_BASE_ENA 0xFFFFFFFB
+#define S_0085F0_SO1_DEST_BASE_ENA(x) (((x) & 0x1) << 3)
+#define G_0085F0_SO1_DEST_BASE_ENA(x) (((x) >> 3) & 0x1)
+#define C_0085F0_SO1_DEST_BASE_ENA 0xFFFFFFF7
+#define S_0085F0_SO2_DEST_BASE_ENA(x) (((x) & 0x1) << 4)
+#define G_0085F0_SO2_DEST_BASE_ENA(x) (((x) >> 4) & 0x1)
+#define C_0085F0_SO2_DEST_BASE_ENA 0xFFFFFFEF
+#define S_0085F0_SO3_DEST_BASE_ENA(x) (((x) & 0x1) << 5)
+#define G_0085F0_SO3_DEST_BASE_ENA(x) (((x) >> 5) & 0x1)
+#define C_0085F0_SO3_DEST_BASE_ENA 0xFFFFFFDF
+#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
+#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
+#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
+#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
+#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
+#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
+#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
+#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
+#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
+#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
+#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
+#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
+#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
+#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
+#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
+#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
+#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
+#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
+#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
+#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
+#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
+#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
+#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
+#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
+#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
+#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
+#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
+#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
+#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
+#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF
+#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
+#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
+#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
+#define S_0085F0_VC_ACTION_ENA(x) (((x) & 0x1) << 24)
+#define G_0085F0_VC_ACTION_ENA(x) (((x) >> 24) & 0x1)
+#define C_0085F0_VC_ACTION_ENA 0xFEFFFFFF
+#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
+#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
+#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF
+#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
+#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
+#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
+#define S_0085F0_SH_ACTION_ENA(x) (((x) & 0x1) << 27)
+#define G_0085F0_SH_ACTION_ENA(x) (((x) >> 27) & 0x1)
+#define C_0085F0_SH_ACTION_ENA 0xF7FFFFFF
+#define S_0085F0_SMX_ACTION_ENA(x) (((x) & 0x1) << 28)
+#define G_0085F0_SMX_ACTION_ENA(x) (((x) >> 28) & 0x1)
+#define C_0085F0_SMX_ACTION_ENA 0xEFFFFFFF
+#define S_0085F0_CR0_ACTION_ENA(x) (((x) & 0x1) << 29)
+#define G_0085F0_CR0_ACTION_ENA(x) (((x) >> 29) & 0x1)
+#define C_0085F0_CR0_ACTION_ENA 0xDFFFFFFF
+#define S_0085F0_CR1_ACTION_ENA(x) (((x) & 0x1) << 30)
+#define G_0085F0_CR1_ACTION_ENA(x) (((x) >> 30) & 0x1)
+#define C_0085F0_CR1_ACTION_ENA 0xBFFFFFFF
+#define S_0085F0_CR2_ACTION_ENA(x) (((x) & 0x1) << 31)
+#define G_0085F0_CR2_ACTION_ENA(x) (((x) >> 31) & 0x1)
+#define C_0085F0_CR2_ACTION_ENA 0x7FFFFFFF
+
+
+#define R_02812C_CB_CLEAR_ALPHA 0x02812C
+#define S_02812C_CLEAR_ALPHA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_02812C_CLEAR_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_02812C_CLEAR_ALPHA 0x00000000
+#define R_028128_CB_CLEAR_BLUE 0x028128
+#define S_028128_CLEAR_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028128_CLEAR_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028128_CLEAR_BLUE 0x00000000
+#define R_028124_CB_CLEAR_GREEN 0x028124
+#define S_028124_CLEAR_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028124_CLEAR_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028124_CLEAR_GREEN 0x00000000
+#define R_028120_CB_CLEAR_RED 0x028120
+#define S_028120_CLEAR_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028120_CLEAR_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028120_CLEAR_RED 0x00000000
+#define R_02842C_CB_FOG_BLUE 0x02842C
+#define S_02842C_FOG_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_02842C_FOG_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_02842C_FOG_BLUE 0x00000000
+#define R_028428_CB_FOG_GREEN 0x028428
+#define S_028428_FOG_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028428_FOG_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028428_FOG_GREEN 0x00000000
+#define R_028424_CB_FOG_RED 0x028424
+#define S_028424_FOG_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_028424_FOG_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_028424_FOG_RED 0x00000000
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0 0x03C000
+#define S_03C000_CLAMP_X(x) (((x) & 0x7) << 0)
+#define G_03C000_CLAMP_X(x) (((x) >> 0) & 0x7)
+#define C_03C000_CLAMP_X 0xFFFFFFF8
+#define S_03C000_CLAMP_Y(x) (((x) & 0x7) << 3)
+#define G_03C000_CLAMP_Y(x) (((x) >> 3) & 0x7)
+#define C_03C000_CLAMP_Y 0xFFFFFFC7
+#define S_03C000_CLAMP_Z(x) (((x) & 0x7) << 6)
+#define G_03C000_CLAMP_Z(x) (((x) >> 6) & 0x7)
+#define C_03C000_CLAMP_Z 0xFFFFFE3F
+#define S_03C000_XY_MAG_FILTER(x) (((x) & 0x7) << 9)
+#define G_03C000_XY_MAG_FILTER(x) (((x) >> 9) & 0x7)
+#define C_03C000_XY_MAG_FILTER 0xFFFFF1FF
+#define S_03C000_XY_MIN_FILTER(x) (((x) & 0x7) << 12)
+#define G_03C000_XY_MIN_FILTER(x) (((x) >> 12) & 0x7)
+#define C_03C000_XY_MIN_FILTER 0xFFFF8FFF
+#define S_03C000_Z_FILTER(x) (((x) & 0x3) << 15)
+#define G_03C000_Z_FILTER(x) (((x) >> 15) & 0x3)
+#define C_03C000_Z_FILTER 0xFFFE7FFF
+#define S_03C000_MIP_FILTER(x) (((x) & 0x3) << 17)
+#define G_03C000_MIP_FILTER(x) (((x) >> 17) & 0x3)
+#define C_03C000_MIP_FILTER 0xFFF9FFFF
+#define S_03C000_BORDER_COLOR_TYPE(x) (((x) & 0x3) << 22)
+#define G_03C000_BORDER_COLOR_TYPE(x) (((x) >> 22) & 0x3)
+#define C_03C000_BORDER_COLOR_TYPE 0xFF3FFFFF
+#define S_03C000_POINT_SAMPLING_CLAMP(x) (((x) & 0x1) << 24)
+#define G_03C000_POINT_SAMPLING_CLAMP(x) (((x) >> 24) & 0x1)
+#define C_03C000_POINT_SAMPLING_CLAMP 0xFEFFFFFF
+#define S_03C000_TEX_ARRAY_OVERRIDE(x) (((x) & 0x1) << 25)
+#define G_03C000_TEX_ARRAY_OVERRIDE(x) (((x) >> 25) & 0x1)
+#define C_03C000_TEX_ARRAY_OVERRIDE 0xFDFFFFFF
+#define S_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) & 0x7) << 26)
+#define G_03C000_DEPTH_COMPARE_FUNCTION(x) (((x) >> 26) & 0x7)
+#define C_03C000_DEPTH_COMPARE_FUNCTION 0xE3FFFFFF
+#define S_03C000_CHROMA_KEY(x) (((x) & 0x3) << 29)
+#define G_03C000_CHROMA_KEY(x) (((x) >> 29) & 0x3)
+#define C_03C000_CHROMA_KEY 0x9FFFFFFF
+#define S_03C000_LOD_USES_MINOR_AXIS(x) (((x) & 0x1) << 31)
+#define G_03C000_LOD_USES_MINOR_AXIS(x) (((x) >> 31) & 0x1)
+#define C_03C000_LOD_USES_MINOR_AXIS 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0 0x03C004
+#define S_03C004_MIN_LOD(x) (((x) & 0x3FF) << 0)
+#define G_03C004_MIN_LOD(x) (((x) >> 0) & 0x3FF)
+#define C_03C004_MIN_LOD 0xFFFFFC00
+#define S_03C004_MAX_LOD(x) (((x) & 0x3FF) << 10)
+#define G_03C004_MAX_LOD(x) (((x) >> 10) & 0x3FF)
+#define C_03C004_MAX_LOD 0xFFF003FF
+#define S_03C004_LOD_BIAS(x) (((x) & 0xFFF) << 20)
+#define G_03C004_LOD_BIAS(x) (((x) >> 20) & 0xFFF)
+#define C_03C004_LOD_BIAS 0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0 0x03C008
+#define S_03C008_LOD_BIAS_SEC(x) (((x) & 0xFFF) << 0)
+#define G_03C008_LOD_BIAS_SEC(x) (((x) >> 0) & 0xFFF)
+#define C_03C008_LOD_BIAS_SEC 0xFFFFF000
+#define S_03C008_MC_COORD_TRUNCATE(x) (((x) & 0x1) << 12)
+#define G_03C008_MC_COORD_TRUNCATE(x) (((x) >> 12) & 0x1)
+#define C_03C008_MC_COORD_TRUNCATE 0xFFFFEFFF
+#define S_03C008_FORCE_DEGAMMA(x) (((x) & 0x1) << 13)
+#define G_03C008_FORCE_DEGAMMA(x) (((x) >> 13) & 0x1)
+#define C_03C008_FORCE_DEGAMMA 0xFFFFDFFF
+#define S_03C008_HIGH_PRECISION_FILTER(x) (((x) & 0x1) << 14)
+#define G_03C008_HIGH_PRECISION_FILTER(x) (((x) >> 14) & 0x1)
+#define C_03C008_HIGH_PRECISION_FILTER 0xFFFFBFFF
+#define S_03C008_PERF_MIP(x) (((x) & 0x7) << 15)
+#define G_03C008_PERF_MIP(x) (((x) >> 15) & 0x7)
+#define C_03C008_PERF_MIP 0xFFFC7FFF
+#define S_03C008_PERF_Z(x) (((x) & 0x3) << 18)
+#define G_03C008_PERF_Z(x) (((x) >> 18) & 0x3)
+#define C_03C008_PERF_Z 0xFFF3FFFF
+#define S_03C008_FETCH_4(x) (((x) & 0x1) << 26)
+#define G_03C008_FETCH_4(x) (((x) >> 26) & 0x1)
+#define C_03C008_FETCH_4 0xFBFFFFFF
+#define S_03C008_SAMPLE_IS_PCF(x) (((x) & 0x1) << 27)
+#define G_03C008_SAMPLE_IS_PCF(x) (((x) >> 27) & 0x1)
+#define C_03C008_SAMPLE_IS_PCF 0xF7FFFFFF
+#define S_03C008_TYPE(x) (((x) & 0x1) << 31)
+#define G_03C008_TYPE(x) (((x) >> 31) & 0x1)
+#define C_03C008_TYPE 0x7FFFFFFF
+#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA 0x00A40C
+#define S_00A40C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A40C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A40C_BORDER_ALPHA 0x00000000
+#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE 0x00A408
+#define S_00A408_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A408_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A408_BORDER_BLUE 0x00000000
+#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN 0x00A404
+#define S_00A404_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A404_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A404_BORDER_GREEN 0x00000000
+#define R_00A400_TD_PS_SAMPLER0_BORDER_RED 0x00A400
+#define S_00A400_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A400_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A400_BORDER_RED 0x00000000
+#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA 0x00A60C
+#define S_00A60C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A60C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A60C_BORDER_ALPHA 0x00000000
+#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE 0x00A608
+#define S_00A608_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A608_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A608_BORDER_BLUE 0x00000000
+#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN 0x00A604
+#define S_00A604_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A604_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A604_BORDER_GREEN 0x00000000
+#define R_00A600_TD_VS_SAMPLER0_BORDER_RED 0x00A600
+#define S_00A600_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A600_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A600_BORDER_RED 0x00000000
+#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA 0x00A80C
+#define S_00A80C_BORDER_ALPHA(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A80C_BORDER_ALPHA(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A80C_BORDER_ALPHA 0x00000000
+#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE 0x00A808
+#define S_00A808_BORDER_BLUE(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A808_BORDER_BLUE(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A808_BORDER_BLUE 0x00000000
+#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN 0x00A804
+#define S_00A804_BORDER_GREEN(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A804_BORDER_GREEN(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A804_BORDER_GREEN 0x00000000
+#define R_00A800_TD_GS_SAMPLER0_BORDER_RED 0x00A800
+#define S_00A800_BORDER_RED(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_00A800_BORDER_RED(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_00A800_BORDER_RED 0x00000000
+#define R_030000_SQ_ALU_CONSTANT0_0 0x030000
+#define S_030000_X(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_030000_X(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_030000_X 0x00000000
+#define R_030004_SQ_ALU_CONSTANT1_0 0x030004
+#define S_030004_Y(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_030004_Y(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_030004_Y 0x00000000
+#define R_030008_SQ_ALU_CONSTANT2_0 0x030008
+#define S_030008_Z(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_030008_Z(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_030008_Z 0x00000000
+#define R_03000C_SQ_ALU_CONSTANT3_0 0x03000C
+#define S_03000C_W(x) (((x) & 0xFFFFFFFF) << 0)
+#define G_03000C_W(x) (((x) >> 0) & 0xFFFFFFFF)
+#define C_03000C_W 0x00000000
+#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4
+#define R_0287E8_VGT_DMA_BASE 0x0287E8
+#define R_028E20_PA_CL_UCP0_X 0x028E20
+#define R_028E24_PA_CL_UCP0_Y 0x028E24
+#define R_028E28_PA_CL_UCP0_Z 0x028E28
+#define R_028E2C_PA_CL_UCP0_W 0x028E2C
+#define R_028E30_PA_CL_UCP1_X 0x028E30
+#define R_028E34_PA_CL_UCP1_Y 0x028E34
+#define R_028E38_PA_CL_UCP1_Z 0x028E38
+#define R_028E3C_PA_CL_UCP1_W 0x028E3C
+#define R_028E40_PA_CL_UCP2_X 0x028E40
+#define R_028E44_PA_CL_UCP2_Y 0x028E44
+#define R_028E48_PA_CL_UCP2_Z 0x028E48
+#define R_028E4C_PA_CL_UCP2_W 0x028E4C
+#define R_028E50_PA_CL_UCP3_X 0x028E50
+#define R_028E54_PA_CL_UCP3_Y 0x028E54
+#define R_028E58_PA_CL_UCP3_Z 0x028E58
+#define R_028E5C_PA_CL_UCP3_W 0x028E5C
+#define R_028E60_PA_CL_UCP4_X 0x028E60
+#define R_028E64_PA_CL_UCP4_Y 0x028E64
+#define R_028E68_PA_CL_UCP4_Z 0x028E68
+#define R_028E6C_PA_CL_UCP4_W 0x028E6C
+#define R_028E70_PA_CL_UCP5_X 0x028E70
+#define R_028E74_PA_CL_UCP5_Y 0x028E74
+#define R_028E78_PA_CL_UCP5_Z 0x028E78
+#define R_028E7C_PA_CL_UCP5_W 0x028E7C
+#define R_038000_RESOURCE0_WORD0 0x038000
+#define R_038004_RESOURCE0_WORD1 0x038004
+#define R_038008_RESOURCE0_WORD2 0x038008
+#define R_03800C_RESOURCE0_WORD3 0x03800C
+#define R_038010_RESOURCE0_WORD4 0x038010
+#define R_038014_RESOURCE0_WORD5 0x038014
+#define R_038018_RESOURCE0_WORD6 0x038018
#define SQ_TEX_INST_LD 0x03
#define SQ_TEX_INST_GET_GRADIENTS_H 0x7
#include "r600/drm/r600_drm_public.h"
#include "r600/r600_public.h"
+#if 1
static struct pipe_screen *
create_screen(int fd)
{
return screen;
}
+#else
+struct radeon *r600_new(int fd, unsigned device);
+struct pipe_screen *r600_screen_create2(struct radeon *radeon);
+static struct pipe_screen *
+create_screen(int fd)
+{
+ struct radeon *radeon;
+ struct pipe_screen *screen;
+
+ radeon = r600_drm_winsys_create(fd);
+ if (!radeon)
+ return NULL;
+
+ screen = r600_screen_create2(radeon);
+ if (!screen)
+ return NULL;
+
+ screen = debug_screen_wrap(screen);
+
+ return screen;
+}
+#endif
DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen)
C_SOURCES = \
bof.c \
r600_state.c \
+ r600_state2.c \
+ r600.c \
radeon_ctx.c \
radeon_draw.c \
radeon_state.c \
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+#include "xf86drm.h"
+#include "radeon_drm.h"
+#include "r600_priv.h"
+
+enum radeon_family r600_get_family(struct radeon *r600)
+{
+ return r600->family;
+}
+
+static int r600_get_device(struct radeon *r600)
+{
+ struct drm_radeon_info info;
+
+ r600->device = 0;
+ info.request = RADEON_INFO_DEVICE_ID;
+ info.value = (uintptr_t)&r600->device;
+ return drmCommandWriteRead(r600->fd, DRM_RADEON_INFO, &info, sizeof(struct drm_radeon_info));
+}
+
+struct radeon *r600_new(int fd, unsigned device)
+{
+ struct radeon *r600;
+ int r;
+
+ r600 = calloc(1, sizeof(*r600));
+ if (r600 == NULL) {
+ return NULL;
+ }
+ r600->fd = fd;
+ r600->device = device;
+ if (fd >= 0) {
+ r = r600_get_device(r600);
+ if (r) {
+ R600_ERR("Failed to get device id\n");
+ r600_delete(r600);
+ return NULL;
+ }
+ }
+ r600->family = radeon_family_from_device(r600->device);
+ if (r600->family == CHIP_UNKNOWN) {
+ R600_ERR("Unknown chipset 0x%04X\n", r600->device);
+ r600_delete(r600);
+ return NULL;
+ }
+ switch (r600->family) {
+ case CHIP_R600:
+ case CHIP_RV610:
+ case CHIP_RV630:
+ case CHIP_RV670:
+ case CHIP_RV620:
+ case CHIP_RV635:
+ case CHIP_RS780:
+ case CHIP_RS880:
+ case CHIP_RV770:
+ case CHIP_RV730:
+ case CHIP_RV710:
+ case CHIP_RV740:
+ break;
+ case CHIP_R100:
+ case CHIP_RV100:
+ case CHIP_RS100:
+ case CHIP_RV200:
+ case CHIP_RS200:
+ case CHIP_R200:
+ case CHIP_RV250:
+ case CHIP_RS300:
+ case CHIP_RV280:
+ case CHIP_R300:
+ case CHIP_R350:
+ case CHIP_RV350:
+ case CHIP_RV380:
+ case CHIP_R420:
+ case CHIP_R423:
+ case CHIP_RV410:
+ case CHIP_RS400:
+ case CHIP_RS480:
+ case CHIP_RS600:
+ case CHIP_RS690:
+ case CHIP_RS740:
+ case CHIP_RV515:
+ case CHIP_R520:
+ case CHIP_RV530:
+ case CHIP_RV560:
+ case CHIP_RV570:
+ case CHIP_R580:
+ case CHIP_CEDAR:
+ case CHIP_REDWOOD:
+ case CHIP_JUNIPER:
+ case CHIP_CYPRESS:
+ case CHIP_HEMLOCK:
+ default:
+ R600_ERR("unknown or unsupported chipset 0x%04X\n", r600->device);
+ break;
+ }
+ return r600;
+}
+
+void r600_delete(struct radeon *r600)
+{
+ if (r600 == NULL)
+ return;
+ drmClose(r600->fd);
+ free(r600);
+}
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+#ifndef R600_PRIV_H
+#define R600_PRIV_H
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "r600.h"
+
+
+struct radeon {
+ int fd;
+ int refcount;
+ unsigned device;
+ unsigned family;
+};
+
+struct radeon *r600_new(int fd, unsigned device);
+void r600_delete(struct radeon *r600);
+
+struct r600_reg {
+ unsigned need_bo;
+ unsigned flush_flags;
+ unsigned offset;
+};
+
+
+/* radeon_pciid.c */
+unsigned radeon_family_from_device(unsigned device);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "r600.h"
+#include "r600d.h"
+#include "r600_priv.h"
+#include "radeon_drm.h"
+#include "bof.h"
+#include "pipe/p_compiler.h"
+#include "util/u_inlines.h"
+#include <pipebuffer/pb_bufmgr.h>
+
+struct radeon_ws_bo {
+ struct pipe_reference reference;
+ struct pb_buffer *pb;
+};
+
+struct radeon_bo {
+ struct pipe_reference reference;
+ unsigned handle;
+ unsigned size;
+ unsigned alignment;
+ unsigned map_count;
+ void *data;
+};
+struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
+int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
+void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
+
+unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo);
+
+static int r600_group_id_register_offset(unsigned offset)
+{
+ if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
+ return R600_GROUP_CONFIG;
+ }
+ if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
+ return R600_GROUP_CONTEXT;
+ }
+ if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
+ return R600_GROUP_ALU_CONST;
+ }
+ if (offset >= R600_RESOURCE_OFFSET && offset < R600_RESOURCE_END) {
+ return R600_GROUP_RESOURCE;
+ }
+ if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
+ return R600_GROUP_SAMPLER;
+ }
+ if (offset >= R600_CTL_CONST_OFFSET && offset < R600_CTL_CONST_END) {
+ return R600_GROUP_CTL_CONST;
+ }
+ if (offset >= R600_LOOP_CONST_OFFSET && offset < R600_LOOP_CONST_END) {
+ return R600_GROUP_LOOP_CONST;
+ }
+ if (offset >= R600_BOOL_CONST_OFFSET && offset < R600_BOOL_CONST_END) {
+ return R600_GROUP_BOOL_CONST;
+ }
+ return -1;
+}
+
+static int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
+{
+ struct r600_group_block *block, *tmp;
+ struct r600_group *group;
+ int group_id, id;
+
+ for (unsigned i = 0, n = 0; i < nreg; i += n) {
+ u32 j, r;
+ /* find number of consecutive registers */
+ for (j = i + 1, r = reg[i].offset + 4, n = 1; j < (nreg - i); j++, n++, r+=4) {
+ if (r != reg[j].offset) {
+ break;
+ }
+ }
+
+ /* find into which group this block is */
+ group_id = r600_group_id_register_offset(reg[i].offset);
+ assert(group_id >= 0);
+ group = &ctx->groups[group_id];
+
+ /* allocate new block */
+ tmp = realloc(group->blocks, (group->nblocks + 1) * sizeof(struct r600_group_block));
+ if (tmp == NULL) {
+ return -ENOMEM;
+ }
+ group->blocks = tmp;
+ block = &group->blocks[group->nblocks++];
+ for (int j = 0; j < n; j++) {
+ group->offset_block_id[((reg[i].offset - group->start_offset) >> 2) + j] = group->nblocks - 1;
+ }
+
+ /* initialize block */
+ memset(block, 0, sizeof(struct r600_group_block));
+ block->start_offset = reg[i].offset;
+ block->pm4_ndwords = n;
+ block->nreg = n;
+ for (j = 0; j < n; j++) {
+ if (reg[i+j].need_bo) {
+ block->nbo++;
+ assert(block->nbo < R600_BLOCK_MAX_BO);
+ block->pm4_bo_index[j] = block->nbo;
+ block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
+ block->pm4[block->pm4_ndwords++] = 0x00000000;
+ block->reloc[block->nbo].bo_pm4_index[block->reloc[block->nbo].nreloc++] = block->pm4_ndwords - 1;
+ }
+ }
+ for (j = 0; j < n; j++) {
+ if (reg[i+j].flush_flags) {
+ block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+ block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags;
+ block->pm4[block->pm4_ndwords++] = 0xFFFFFFFF;
+ block->pm4[block->pm4_ndwords++] = 0x00000000;
+ block->pm4[block->pm4_ndwords++] = 0x0000000A;
+ block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0);
+ block->pm4[block->pm4_ndwords++] = 0x00000000;
+ id = block->pm4_bo_index[j];
+ block->reloc[id].bo_pm4_index[block->reloc[id].nreloc++] = block->pm4_ndwords - 1;
+ }
+ }
+ /* check that we stay in limit */
+ assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
+ }
+ return 0;
+}
+
+static int r600_group_init(struct r600_group *group, unsigned start_offset, unsigned end_offset)
+{
+ group->start_offset = start_offset;
+ group->end_offset = end_offset;
+ group->nblocks = 0;
+ group->blocks = NULL;
+ group->offset_block_id = calloc((end_offset - start_offset) >> 2, sizeof(unsigned));
+ if (group->offset_block_id == NULL)
+ return -ENOMEM;
+ return 0;
+}
+
+static void r600_group_fini(struct r600_group *group)
+{
+ free(group->offset_block_id);
+ free(group->blocks);
+}
+
+/* R600/R700 configuration */
+static const struct r600_reg r600_reg_list[] = {
+ {0, 0, R_008C00_SQ_CONFIG},
+ {0, 0, R_008C04_SQ_GPR_RESOURCE_MGMT_1},
+ {0, 0, R_008C08_SQ_GPR_RESOURCE_MGMT_2},
+ {0, 0, R_008C0C_SQ_THREAD_RESOURCE_MGMT},
+ {0, 0, R_008C10_SQ_STACK_RESOURCE_MGMT_1},
+ {0, 0, R_008C14_SQ_STACK_RESOURCE_MGMT_2},
+ {0, 0, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ},
+ {0, 0, R_009508_TA_CNTL_AUX},
+ {0, 0, R_009714_VC_ENHANCE},
+ {0, 0, R_009830_DB_DEBUG},
+ {0, 0, R_009838_DB_WATERMARKS},
+ {0, 0, R_028350_SX_MISC},
+ {0, 0, R_0286C8_SPI_THREAD_GROUPING},
+ {0, 0, R_0288A8_SQ_ESGS_RING_ITEMSIZE},
+ {0, 0, R_0288AC_SQ_GSVS_RING_ITEMSIZE},
+ {0, 0, R_0288B0_SQ_ESTMP_RING_ITEMSIZE},
+ {0, 0, R_0288B4_SQ_GSTMP_RING_ITEMSIZE},
+ {0, 0, R_0288B8_SQ_VSTMP_RING_ITEMSIZE},
+ {0, 0, R_0288BC_SQ_PSTMP_RING_ITEMSIZE},
+ {0, 0, R_0288C0_SQ_FBUF_RING_ITEMSIZE},
+ {0, 0, R_0288C4_SQ_REDUC_RING_ITEMSIZE},
+ {0, 0, R_0288C8_SQ_GS_VERT_ITEMSIZE},
+ {0, 0, R_028A10_VGT_OUTPUT_PATH_CNTL},
+ {0, 0, R_028A14_VGT_HOS_CNTL},
+ {0, 0, R_028A18_VGT_HOS_MAX_TESS_LEVEL},
+ {0, 0, R_028A1C_VGT_HOS_MIN_TESS_LEVEL},
+ {0, 0, R_028A20_VGT_HOS_REUSE_DEPTH},
+ {0, 0, R_028A24_VGT_GROUP_PRIM_TYPE},
+ {0, 0, R_028A28_VGT_GROUP_FIRST_DECR},
+ {0, 0, R_028A2C_VGT_GROUP_DECR},
+ {0, 0, R_028A30_VGT_GROUP_VECT_0_CNTL},
+ {0, 0, R_028A34_VGT_GROUP_VECT_1_CNTL},
+ {0, 0, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL},
+ {0, 0, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL},
+ {0, 0, R_028A40_VGT_GS_MODE},
+ {0, 0, R_028A4C_PA_SC_MODE_CNTL},
+ {0, 0, R_028AB0_VGT_STRMOUT_EN},
+ {0, 0, R_028AB4_VGT_REUSE_OFF},
+ {0, 0, R_028AB8_VGT_VTX_CNT_EN},
+ {0, 0, R_028B20_VGT_STRMOUT_BUFFER_EN},
+ {0, 0, R_028028_DB_STENCIL_CLEAR},
+ {0, 0, R_02802C_DB_DEPTH_CLEAR},
+ {1, 0, R_028040_CB_COLOR0_BASE},
+ {0, 0, R_0280A0_CB_COLOR0_INFO},
+ {0, 0, R_028060_CB_COLOR0_SIZE},
+ {0, 0, R_028080_CB_COLOR0_VIEW},
+ {1, 0, R_0280E0_CB_COLOR0_FRAG},
+ {1, 0, R_0280C0_CB_COLOR0_TILE},
+ {0, 0, R_028100_CB_COLOR0_MASK},
+ {1, 0, R_028044_CB_COLOR1_BASE},
+ {0, 0, R_0280A4_CB_COLOR1_INFO},
+ {0, 0, R_028064_CB_COLOR1_SIZE},
+ {0, 0, R_028084_CB_COLOR1_VIEW},
+ {1, 0, R_0280E4_CB_COLOR1_FRAG},
+ {1, 0, R_0280C4_CB_COLOR1_TILE},
+ {0, 0, R_028104_CB_COLOR1_MASK},
+ {1, 0, R_028048_CB_COLOR2_BASE},
+ {0, 0, R_0280A8_CB_COLOR2_INFO},
+ {0, 0, R_028068_CB_COLOR2_SIZE},
+ {0, 0, R_028088_CB_COLOR2_VIEW},
+ {1, 0, R_0280E8_CB_COLOR2_FRAG},
+ {1, 0, R_0280C8_CB_COLOR2_TILE},
+ {0, 0, R_028108_CB_COLOR2_MASK},
+ {1, 0, R_02804C_CB_COLOR3_BASE},
+ {0, 0, R_0280AC_CB_COLOR3_INFO},
+ {0, 0, R_02806C_CB_COLOR3_SIZE},
+ {0, 0, R_02808C_CB_COLOR3_VIEW},
+ {1, 0, R_0280EC_CB_COLOR3_FRAG},
+ {1, 0, R_0280CC_CB_COLOR3_TILE},
+ {0, 0, R_02810C_CB_COLOR3_MASK},
+ {1, 0, R_028050_CB_COLOR4_BASE},
+ {0, 0, R_0280B0_CB_COLOR4_INFO},
+ {0, 0, R_028070_CB_COLOR4_SIZE},
+ {0, 0, R_028090_CB_COLOR4_VIEW},
+ {1, 0, R_0280F0_CB_COLOR4_FRAG},
+ {1, 0, R_0280D0_CB_COLOR4_TILE},
+ {0, 0, R_028110_CB_COLOR4_MASK},
+ {1, 0, R_028054_CB_COLOR5_BASE},
+ {0, 0, R_0280B4_CB_COLOR5_INFO},
+ {0, 0, R_028074_CB_COLOR5_SIZE},
+ {0, 0, R_028094_CB_COLOR5_VIEW},
+ {1, 0, R_0280F4_CB_COLOR5_FRAG},
+ {1, 0, R_0280D4_CB_COLOR5_TILE},
+ {0, 0, R_028114_CB_COLOR5_MASK},
+ {1, 0, R_028058_CB_COLOR6_BASE},
+ {0, 0, R_0280B8_CB_COLOR6_INFO},
+ {0, 0, R_028078_CB_COLOR6_SIZE},
+ {0, 0, R_028098_CB_COLOR6_VIEW},
+ {1, 0, R_0280F8_CB_COLOR6_FRAG},
+ {1, 0, R_0280D8_CB_COLOR6_TILE},
+ {0, 0, R_028118_CB_COLOR6_MASK},
+ {1, 0, R_02805C_CB_COLOR7_BASE},
+ {0, 0, R_0280BC_CB_COLOR7_INFO},
+ {0, 0, R_02807C_CB_COLOR7_SIZE},
+ {0, 0, R_02809C_CB_COLOR7_VIEW},
+ {1, 0, R_0280FC_CB_COLOR7_FRAG},
+ {1, 0, R_0280DC_CB_COLOR7_TILE},
+ {0, 0, R_02811C_CB_COLOR7_MASK},
+ {0, 0, R_028120_CB_CLEAR_RED},
+ {0, 0, R_028124_CB_CLEAR_GREEN},
+ {0, 0, R_028128_CB_CLEAR_BLUE},
+ {0, 0, R_02812C_CB_CLEAR_ALPHA},
+ {0, 0, R_02823C_CB_SHADER_MASK},
+ {0, 0, R_028238_CB_TARGET_MASK},
+ {0, 0, R_028410_SX_ALPHA_TEST_CONTROL},
+ {0, 0, R_028414_CB_BLEND_RED},
+ {0, 0, R_028418_CB_BLEND_GREEN},
+ {0, 0, R_02841C_CB_BLEND_BLUE},
+ {0, 0, R_028420_CB_BLEND_ALPHA},
+ {0, 0, R_028424_CB_FOG_RED},
+ {0, 0, R_028428_CB_FOG_GREEN},
+ {0, 0, R_02842C_CB_FOG_BLUE},
+ {0, 0, R_028430_DB_STENCILREFMASK},
+ {0, 0, R_028434_DB_STENCILREFMASK_BF},
+ {0, 0, R_028438_SX_ALPHA_REF},
+ {0, 0, R_0286DC_SPI_FOG_CNTL},
+ {0, 0, R_0286E0_SPI_FOG_FUNC_SCALE},
+ {0, 0, R_0286E4_SPI_FOG_FUNC_BIAS},
+ {0, 0, R_028780_CB_BLEND0_CONTROL},
+ {0, 0, R_028784_CB_BLEND1_CONTROL},
+ {0, 0, R_028788_CB_BLEND2_CONTROL},
+ {0, 0, R_02878C_CB_BLEND3_CONTROL},
+ {0, 0, R_028790_CB_BLEND4_CONTROL},
+ {0, 0, R_028794_CB_BLEND5_CONTROL},
+ {0, 0, R_028798_CB_BLEND6_CONTROL},
+ {0, 0, R_02879C_CB_BLEND7_CONTROL},
+ {0, 0, R_0287A0_CB_SHADER_CONTROL},
+ {0, 0, R_028800_DB_DEPTH_CONTROL},
+ {0, 0, R_028804_CB_BLEND_CONTROL},
+ {0, 0, R_028808_CB_COLOR_CONTROL},
+ {0, 0, R_02880C_DB_SHADER_CONTROL},
+ {0, 0, R_028C04_PA_SC_AA_CONFIG},
+ {0, 0, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX},
+ {0, 0, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX},
+ {0, 0, R_028C30_CB_CLRCMP_CONTROL},
+ {0, 0, R_028C34_CB_CLRCMP_SRC},
+ {0, 0, R_028C38_CB_CLRCMP_DST},
+ {0, 0, R_028C3C_CB_CLRCMP_MSK},
+ {0, 0, R_028C48_PA_SC_AA_MASK},
+ {0, 0, R_028D2C_DB_SRESULTS_COMPARE_STATE1},
+ {0, 0, R_028D44_DB_ALPHA_TO_MASK},
+ {1, 0, R_02800C_DB_DEPTH_BASE},
+ {0, 0, R_028000_DB_DEPTH_SIZE},
+ {0, 0, R_028004_DB_DEPTH_VIEW},
+ {0, 0, R_028010_DB_DEPTH_INFO},
+ {0, 0, R_028D0C_DB_RENDER_CONTROL},
+ {0, 0, R_028D10_DB_RENDER_OVERRIDE},
+ {0, 0, R_028D24_DB_HTILE_SURFACE},
+ {0, 0, R_028D30_DB_PRELOAD_CONTROL},
+ {0, 0, R_028D34_DB_PREFETCH_LIMIT},
+ {0, 0, R_028030_PA_SC_SCREEN_SCISSOR_TL},
+ {0, 0, R_028034_PA_SC_SCREEN_SCISSOR_BR},
+ {0, 0, R_028200_PA_SC_WINDOW_OFFSET},
+ {0, 0, R_028204_PA_SC_WINDOW_SCISSOR_TL},
+ {0, 0, R_028208_PA_SC_WINDOW_SCISSOR_BR},
+ {0, 0, R_02820C_PA_SC_CLIPRECT_RULE},
+ {0, 0, R_028210_PA_SC_CLIPRECT_0_TL},
+ {0, 0, R_028214_PA_SC_CLIPRECT_0_BR},
+ {0, 0, R_028218_PA_SC_CLIPRECT_1_TL},
+ {0, 0, R_02821C_PA_SC_CLIPRECT_1_BR},
+ {0, 0, R_028220_PA_SC_CLIPRECT_2_TL},
+ {0, 0, R_028224_PA_SC_CLIPRECT_2_BR},
+ {0, 0, R_028228_PA_SC_CLIPRECT_3_TL},
+ {0, 0, R_02822C_PA_SC_CLIPRECT_3_BR},
+ {0, 0, R_028230_PA_SC_EDGERULE},
+ {0, 0, R_028240_PA_SC_GENERIC_SCISSOR_TL},
+ {0, 0, R_028244_PA_SC_GENERIC_SCISSOR_BR},
+ {0, 0, R_028250_PA_SC_VPORT_SCISSOR_0_TL},
+ {0, 0, R_028254_PA_SC_VPORT_SCISSOR_0_BR},
+ {0, 0, R_0282D0_PA_SC_VPORT_ZMIN_0},
+ {0, 0, R_0282D4_PA_SC_VPORT_ZMAX_0},
+ {0, 0, R_02843C_PA_CL_VPORT_XSCALE_0},
+ {0, 0, R_028440_PA_CL_VPORT_XOFFSET_0},
+ {0, 0, R_028444_PA_CL_VPORT_YSCALE_0},
+ {0, 0, R_028448_PA_CL_VPORT_YOFFSET_0},
+ {0, 0, R_02844C_PA_CL_VPORT_ZSCALE_0},
+ {0, 0, R_028450_PA_CL_VPORT_ZOFFSET_0},
+ {0, 0, R_0286D4_SPI_INTERP_CONTROL_0},
+ {0, 0, R_028810_PA_CL_CLIP_CNTL},
+ {0, 0, R_028814_PA_SU_SC_MODE_CNTL},
+ {0, 0, R_028818_PA_CL_VTE_CNTL},
+ {0, 0, R_02881C_PA_CL_VS_OUT_CNTL},
+ {0, 0, R_028820_PA_CL_NANINF_CNTL},
+ {0, 0, R_028A00_PA_SU_POINT_SIZE},
+ {0, 0, R_028A04_PA_SU_POINT_MINMAX},
+ {0, 0, R_028A08_PA_SU_LINE_CNTL},
+ {0, 0, R_028A0C_PA_SC_LINE_STIPPLE},
+ {0, 0, R_028A48_PA_SC_MPASS_PS_CNTL},
+ {0, 0, R_028C00_PA_SC_LINE_CNTL},
+ {0, 0, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ},
+ {0, 0, R_028C10_PA_CL_GB_VERT_DISC_ADJ},
+ {0, 0, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ},
+ {0, 0, R_028C18_PA_CL_GB_HORZ_DISC_ADJ},
+ {0, 0, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL},
+ {0, 0, R_028DFC_PA_SU_POLY_OFFSET_CLAMP},
+ {0, 0, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE},
+ {0, 0, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET},
+ {0, 0, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE},
+ {0, 0, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET},
+ {0, 0, R_028E20_PA_CL_UCP0_X},
+ {0, 0, R_028E24_PA_CL_UCP0_Y},
+ {0, 0, R_028E28_PA_CL_UCP0_Z},
+ {0, 0, R_028E2C_PA_CL_UCP0_W},
+ {0, 0, R_028E30_PA_CL_UCP1_X},
+ {0, 0, R_028E34_PA_CL_UCP1_Y},
+ {0, 0, R_028E38_PA_CL_UCP1_Z},
+ {0, 0, R_028E3C_PA_CL_UCP1_W},
+ {0, 0, R_028E40_PA_CL_UCP2_X},
+ {0, 0, R_028E44_PA_CL_UCP2_Y},
+ {0, 0, R_028E48_PA_CL_UCP2_Z},
+ {0, 0, R_028E4C_PA_CL_UCP2_W},
+ {0, 0, R_028E50_PA_CL_UCP3_X},
+ {0, 0, R_028E54_PA_CL_UCP3_Y},
+ {0, 0, R_028E58_PA_CL_UCP3_Z},
+ {0, 0, R_028E5C_PA_CL_UCP3_W},
+ {0, 0, R_028E60_PA_CL_UCP4_X},
+ {0, 0, R_028E64_PA_CL_UCP4_Y},
+ {0, 0, R_028E68_PA_CL_UCP4_Z},
+ {0, 0, R_028E6C_PA_CL_UCP4_W},
+ {0, 0, R_028E70_PA_CL_UCP5_X},
+ {0, 0, R_028E74_PA_CL_UCP5_Y},
+ {0, 0, R_028E78_PA_CL_UCP5_Z},
+ {0, 0, R_028E7C_PA_CL_UCP5_W},
+ {0, 0, R_028380_SQ_VTX_SEMANTIC_0},
+ {0, 0, R_028384_SQ_VTX_SEMANTIC_1},
+ {0, 0, R_028388_SQ_VTX_SEMANTIC_2},
+ {0, 0, R_02838C_SQ_VTX_SEMANTIC_3},
+ {0, 0, R_028390_SQ_VTX_SEMANTIC_4},
+ {0, 0, R_028394_SQ_VTX_SEMANTIC_5},
+ {0, 0, R_028398_SQ_VTX_SEMANTIC_6},
+ {0, 0, R_02839C_SQ_VTX_SEMANTIC_7},
+ {0, 0, R_0283A0_SQ_VTX_SEMANTIC_8},
+ {0, 0, R_0283A4_SQ_VTX_SEMANTIC_9},
+ {0, 0, R_0283A8_SQ_VTX_SEMANTIC_10},
+ {0, 0, R_0283AC_SQ_VTX_SEMANTIC_11},
+ {0, 0, R_0283B0_SQ_VTX_SEMANTIC_12},
+ {0, 0, R_0283B4_SQ_VTX_SEMANTIC_13},
+ {0, 0, R_0283B8_SQ_VTX_SEMANTIC_14},
+ {0, 0, R_0283BC_SQ_VTX_SEMANTIC_15},
+ {0, 0, R_0283C0_SQ_VTX_SEMANTIC_16},
+ {0, 0, R_0283C4_SQ_VTX_SEMANTIC_17},
+ {0, 0, R_0283C8_SQ_VTX_SEMANTIC_18},
+ {0, 0, R_0283CC_SQ_VTX_SEMANTIC_19},
+ {0, 0, R_0283D0_SQ_VTX_SEMANTIC_20},
+ {0, 0, R_0283D4_SQ_VTX_SEMANTIC_21},
+ {0, 0, R_0283D8_SQ_VTX_SEMANTIC_22},
+ {0, 0, R_0283DC_SQ_VTX_SEMANTIC_23},
+ {0, 0, R_0283E0_SQ_VTX_SEMANTIC_24},
+ {0, 0, R_0283E4_SQ_VTX_SEMANTIC_25},
+ {0, 0, R_0283E8_SQ_VTX_SEMANTIC_26},
+ {0, 0, R_0283EC_SQ_VTX_SEMANTIC_27},
+ {0, 0, R_0283F0_SQ_VTX_SEMANTIC_28},
+ {0, 0, R_0283F4_SQ_VTX_SEMANTIC_29},
+ {0, 0, R_0283F8_SQ_VTX_SEMANTIC_30},
+ {0, 0, R_0283FC_SQ_VTX_SEMANTIC_31},
+ {0, 0, R_028614_SPI_VS_OUT_ID_0},
+ {0, 0, R_028618_SPI_VS_OUT_ID_1},
+ {0, 0, R_02861C_SPI_VS_OUT_ID_2},
+ {0, 0, R_028620_SPI_VS_OUT_ID_3},
+ {0, 0, R_028624_SPI_VS_OUT_ID_4},
+ {0, 0, R_028628_SPI_VS_OUT_ID_5},
+ {0, 0, R_02862C_SPI_VS_OUT_ID_6},
+ {0, 0, R_028630_SPI_VS_OUT_ID_7},
+ {0, 0, R_028634_SPI_VS_OUT_ID_8},
+ {0, 0, R_028638_SPI_VS_OUT_ID_9},
+ {0, 0, R_0286C4_SPI_VS_OUT_CONFIG},
+ {1, 0, R_028858_SQ_PGM_START_VS},
+ {0, S_0085F0_SH_ACTION_ENA(1), R_028868_SQ_PGM_RESOURCES_VS},
+ {1, 0, R_028894_SQ_PGM_START_FS},
+ {0, S_0085F0_SH_ACTION_ENA(1), R_0288A4_SQ_PGM_RESOURCES_FS},
+ {0, 0, R_0288D0_SQ_PGM_CF_OFFSET_VS},
+ {0, 0, R_0288DC_SQ_PGM_CF_OFFSET_FS},
+ {0, 0, R_028644_SPI_PS_INPUT_CNTL_0},
+ {0, 0, R_028648_SPI_PS_INPUT_CNTL_1},
+ {0, 0, R_02864C_SPI_PS_INPUT_CNTL_2},
+ {0, 0, R_028650_SPI_PS_INPUT_CNTL_3},
+ {0, 0, R_028654_SPI_PS_INPUT_CNTL_4},
+ {0, 0, R_028658_SPI_PS_INPUT_CNTL_5},
+ {0, 0, R_02865C_SPI_PS_INPUT_CNTL_6},
+ {0, 0, R_028660_SPI_PS_INPUT_CNTL_7},
+ {0, 0, R_028664_SPI_PS_INPUT_CNTL_8},
+ {0, 0, R_028668_SPI_PS_INPUT_CNTL_9},
+ {0, 0, R_02866C_SPI_PS_INPUT_CNTL_10},
+ {0, 0, R_028670_SPI_PS_INPUT_CNTL_11},
+ {0, 0, R_028674_SPI_PS_INPUT_CNTL_12},
+ {0, 0, R_028678_SPI_PS_INPUT_CNTL_13},
+ {0, 0, R_02867C_SPI_PS_INPUT_CNTL_14},
+ {0, 0, R_028680_SPI_PS_INPUT_CNTL_15},
+ {0, 0, R_028684_SPI_PS_INPUT_CNTL_16},
+ {0, 0, R_028688_SPI_PS_INPUT_CNTL_17},
+ {0, 0, R_02868C_SPI_PS_INPUT_CNTL_18},
+ {0, 0, R_028690_SPI_PS_INPUT_CNTL_19},
+ {0, 0, R_028694_SPI_PS_INPUT_CNTL_20},
+ {0, 0, R_028698_SPI_PS_INPUT_CNTL_21},
+ {0, 0, R_02869C_SPI_PS_INPUT_CNTL_22},
+ {0, 0, R_0286A0_SPI_PS_INPUT_CNTL_23},
+ {0, 0, R_0286A4_SPI_PS_INPUT_CNTL_24},
+ {0, 0, R_0286A8_SPI_PS_INPUT_CNTL_25},
+ {0, 0, R_0286AC_SPI_PS_INPUT_CNTL_26},
+ {0, 0, R_0286B0_SPI_PS_INPUT_CNTL_27},
+ {0, 0, R_0286B4_SPI_PS_INPUT_CNTL_28},
+ {0, 0, R_0286B8_SPI_PS_INPUT_CNTL_29},
+ {0, 0, R_0286BC_SPI_PS_INPUT_CNTL_30},
+ {0, 0, R_0286C0_SPI_PS_INPUT_CNTL_31},
+ {0, 0, R_0286CC_SPI_PS_IN_CONTROL_0},
+ {0, 0, R_0286D0_SPI_PS_IN_CONTROL_1},
+ {0, 0, R_0286D8_SPI_INPUT_Z},
+ {1, S_0085F0_SH_ACTION_ENA(1), R_028840_SQ_PGM_START_PS},
+ {0, 0, R_028850_SQ_PGM_RESOURCES_PS},
+ {0, 0, R_028854_SQ_PGM_EXPORTS_PS},
+ {0, 0, R_0288CC_SQ_PGM_CF_OFFSET_PS},
+ {0, 0, R_008958_VGT_PRIMITIVE_TYPE},
+ {0, 0, R_028400_VGT_MAX_VTX_INDX},
+ {0, 0, R_028404_VGT_MIN_VTX_INDX},
+ {0, 0, R_028408_VGT_INDX_OFFSET},
+ {0, 0, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX},
+ {0, 0, R_028A84_VGT_PRIMITIVEID_EN},
+ {0, 0, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN},
+ {0, 0, R_028AA0_VGT_INSTANCE_STEP_RATE_0},
+ {0, 0, R_028AA4_VGT_INSTANCE_STEP_RATE_1},
+};
+
+/* SHADER CONSTANT R600/R700 */
+static int r600_state_constant_init(struct r600_context *ctx, u32 offset)
+{
+ struct r600_reg r600_shader_constant[] = {
+ {0, 0, R_030000_SQ_ALU_CONSTANT0_0},
+ {0, 0, R_030004_SQ_ALU_CONSTANT1_0},
+ {0, 0, R_030008_SQ_ALU_CONSTANT2_0},
+ {0, 0, R_03000C_SQ_ALU_CONSTANT3_0},
+ };
+ unsigned nreg = sizeof(r600_shader_constant)/sizeof(struct r600_reg);
+
+ for (int i = 0; i < nreg; i++) {
+ r600_shader_constant[i].offset += offset;
+ }
+ return r600_context_add_block(ctx, r600_shader_constant, nreg);
+}
+
+/* SHADER RESOURCE R600/R700 */
+static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
+{
+ struct r600_reg r600_shader_resource[] = {
+ {0, 0, R_038000_RESOURCE0_WORD0},
+ {0, 0, R_038004_RESOURCE0_WORD1},
+ {1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), R_038008_RESOURCE0_WORD2},
+ {1, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), R_03800C_RESOURCE0_WORD3},
+ {0, 0, R_038010_RESOURCE0_WORD4},
+ {0, 0, R_038014_RESOURCE0_WORD5},
+ {0, 0, R_038018_RESOURCE0_WORD6},
+ };
+ unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
+
+ for (int i = 0; i < nreg; i++) {
+ r600_shader_resource[i].offset += offset;
+ }
+ return r600_context_add_block(ctx, r600_shader_resource, nreg);
+}
+
+/* SHADER SAMPLER R600/R700 */
+static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+{
+ struct r600_reg r600_shader_sampler[] = {
+ {0, 0, R_03C000_SQ_TEX_SAMPLER_WORD0_0},
+ {0, 0, R_03C004_SQ_TEX_SAMPLER_WORD1_0},
+ {0, 0, R_03C008_SQ_TEX_SAMPLER_WORD2_0},
+ };
+ unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
+
+ for (int i = 0; i < nreg; i++) {
+ r600_shader_sampler[i].offset += offset;
+ }
+ return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+}
+
+/* SHADER SAMPLER BORDER R600/R700 */
+static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
+{
+ struct r600_reg r600_shader_sampler_border[] = {
+ {0, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED},
+ {0, 0, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN},
+ {0, 0, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE},
+ {0, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA},
+ };
+ unsigned nreg = sizeof(r600_shader_sampler_border)/sizeof(struct r600_reg);
+
+ for (int i = 0; i < nreg; i++) {
+ r600_shader_sampler_border[i].offset += offset;
+ }
+ return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
+}
+
+/* initialize */
+void r600_context_fini(struct r600_context *ctx)
+{
+ for (int i = 0; i < ctx->ngroups; i++) {
+ r600_group_fini(&ctx->groups[i]);
+ }
+ free(ctx->reloc);
+ free(ctx->pm4);
+ memset(ctx, 0, sizeof(struct r600_context));
+}
+
+int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
+{
+ int r;
+
+ memset(ctx, 0, sizeof(struct r600_context));
+ ctx->radeon = radeon;
+ /* initialize groups */
+ r = r600_group_init(&ctx->groups[R600_GROUP_CONFIG], R600_CONFIG_REG_OFFSET, R600_CONFIG_REG_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_CTL_CONST], R600_CTL_CONST_OFFSET, R600_CTL_CONST_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_LOOP_CONST], R600_LOOP_CONST_OFFSET, R600_LOOP_CONST_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_BOOL_CONST], R600_BOOL_CONST_OFFSET, R600_BOOL_CONST_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_SAMPLER], R600_SAMPLER_OFFSET, R600_SAMPLER_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_RESOURCE], R600_RESOURCE_OFFSET, R600_RESOURCE_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_ALU_CONST], R600_ALU_CONST_OFFSET, R600_ALU_CONST_END);
+ if (r) {
+ goto out_err;
+ }
+ r = r600_group_init(&ctx->groups[R600_GROUP_CONTEXT], R600_CONTEXT_REG_OFFSET, R600_CONTEXT_REG_END);
+ if (r) {
+ goto out_err;
+ }
+ ctx->ngroups = R600_NGROUPS;
+
+ /* add blocks */
+ r = r600_context_add_block(ctx, r600_reg_list, sizeof(r600_reg_list)/sizeof(struct r600_reg));
+ if (r)
+ goto out_err;
+
+ /* PS SAMPLER BORDER */
+ for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
+ r = r600_state_sampler_border_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+
+ /* VS SAMPLER BORDER */
+ for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
+ r = r600_state_sampler_border_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* PS SAMPLER */
+ for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
+ r = r600_state_sampler_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* VS SAMPLER */
+ for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
+ r = r600_state_sampler_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* PS RESOURCE */
+ for (int j = 0, offset = 0; j < 160; j++, offset += 0x1C) {
+ r = r600_state_resource_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* VS RESOURCE */
+ for (int j = 0, offset = 0x1180; j < 160; j++, offset += 0x1C) {
+ r = r600_state_resource_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* PS CONSTANT */
+ for (int j = 0, offset = 0; j < 256; j++, offset += 0x10) {
+ r = r600_state_constant_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+ /* VS CONSTANT */
+ for (int j = 0, offset = 0x1000; j < 256; j++, offset += 0x10) {
+ r = r600_state_constant_init(ctx, offset);
+ if (r)
+ goto out_err;
+ }
+
+ /* allocate cs variables */
+ ctx->nreloc = RADEON_CTX_MAX_PM4;
+ ctx->reloc = calloc(ctx->nreloc, sizeof(struct r600_reloc));
+ if (ctx->reloc == NULL) {
+ r = -ENOMEM;
+ goto out_err;
+ }
+ ctx->bo = calloc(ctx->nreloc, sizeof(void *));
+ if (ctx->bo == NULL) {
+ r = -ENOMEM;
+ goto out_err;
+ }
+ ctx->pm4_ndwords = RADEON_CTX_MAX_PM4;
+ ctx->pm4 = calloc(ctx->pm4_ndwords, 4);
+ if (ctx->pm4 == NULL) {
+ r = -ENOMEM;
+ goto out_err;
+ }
+ return 0;
+out_err:
+ r600_context_fini(ctx);
+ return r;
+}
+
+static void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct radeon_ws_bo *bo)
+{
+ int i, reloc_id;
+ unsigned handle = radeon_ws_bo_get_handle(bo);
+
+ assert(bo != NULL);
+ for (i = 0, reloc_id = -1; i < ctx->creloc; i++) {
+ if (ctx->reloc[i].handle == handle) {
+ reloc_id = i * sizeof(struct r600_reloc) / 4;
+ /* set PKT3 to point to proper reloc */
+ *pm4 = reloc_id;
+ }
+ }
+ if (reloc_id == -1) {
+ /* add new relocation */
+ if (ctx->creloc >= ctx->nreloc) {
+ r600_context_flush(ctx);
+ }
+ reloc_id = ctx->creloc * sizeof(struct r600_reloc) / 4;
+ ctx->reloc[ctx->creloc].handle = handle;
+ ctx->reloc[ctx->creloc].read_domain = RADEON_GEM_DOMAIN_GTT;
+ ctx->reloc[ctx->creloc].write_domain = RADEON_GEM_DOMAIN_GTT;
+ ctx->reloc[ctx->creloc].flags = 0;
+ radeon_ws_bo_reference(ctx->radeon, &ctx->bo[ctx->creloc], bo);
+ ctx->creloc++;
+ /* set PKT3 to point to proper reloc */
+ *pm4 = reloc_id;
+ }
+}
+
+void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
+{
+ struct r600_group *group;
+ struct r600_group_block *block;
+
+ for (int i = 0; i < state->nregs; i++) {
+ unsigned id;
+ group = &ctx->groups[state->regs[i].group_id];
+ id = group->offset_block_id[(state->regs[i].offset - group->start_offset) >> 2];
+ block = &group->blocks[id];
+ id = (state->regs[i].offset - block->start_offset) >> 2;
+ block->pm4[id] &= ~state->regs[i].mask;
+ block->pm4[id] |= state->regs[i].value;
+ if (block->pm4_bo_index[id]) {
+ /* find relocation */
+ id = block->pm4_bo_index[id];
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[id].bo, state->regs[i].bo);
+ for (int j = 0; j < block->reloc[id].nreloc; j++) {
+ r600_context_bo_reloc(ctx, &block->pm4[block->reloc[id].bo_pm4_index[j]],
+ block->reloc[id].bo);
+ }
+ }
+ block->status |= R600_BLOCK_STATUS_ENABLED;
+ block->status |= R600_BLOCK_STATUS_DIRTY;
+ ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+ }
+}
+
+static inline void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+ struct r600_group_block *block;
+ unsigned id;
+
+ offset -= ctx->groups[R600_GROUP_RESOURCE].start_offset;
+ id = ctx->groups[R600_GROUP_RESOURCE].offset_block_id[offset >> 2];
+ block = &ctx->groups[R600_GROUP_RESOURCE].blocks[id];
+ block->pm4[0] = state->regs[0].value;
+ block->pm4[1] = state->regs[1].value;
+ block->pm4[2] = state->regs[2].value;
+ block->pm4[3] = state->regs[3].value;
+ block->pm4[4] = state->regs[4].value;
+ block->pm4[5] = state->regs[5].value;
+ block->pm4[6] = state->regs[6].value;
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, block->reloc[1].bo);
+ radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, block->reloc[2].bo);
+ if (state->regs[0].bo) {
+ /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
+ * we have single case btw VERTEX & TEXTURE resource
+ */
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo);
+ } else {
+ /* TEXTURE RESOURCE */
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo);
+ radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
+ }
+ r600_context_bo_reloc(ctx, &block->pm4[block->reloc[1].bo_pm4_index[0]], block->reloc[1].bo);
+ r600_context_bo_reloc(ctx, &block->pm4[block->reloc[2].bo_pm4_index[0]], block->reloc[2].bo);
+ block->status |= R600_BLOCK_STATUS_ENABLED;
+ block->status |= R600_BLOCK_STATUS_DIRTY;
+ ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+ unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1C * rid;
+
+ r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+ unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x1180 + 0x1C * rid;
+
+ r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
+static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+ struct r600_group_block *block;
+ unsigned id;
+
+ offset -= ctx->groups[R600_GROUP_SAMPLER].start_offset;
+ id = ctx->groups[R600_GROUP_SAMPLER].offset_block_id[offset >> 2];
+ block = &ctx->groups[R600_GROUP_SAMPLER].blocks[id];
+ block->pm4[0] = state->regs[0].value;
+ block->pm4[1] = state->regs[1].value;
+ block->pm4[2] = state->regs[2].value;
+ block->status |= R600_BLOCK_STATUS_ENABLED;
+ block->status |= R600_BLOCK_STATUS_DIRTY;
+ ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
+{
+ struct r600_group_block *block;
+ unsigned id;
+
+ offset -= ctx->groups[R600_GROUP_CONFIG].start_offset;
+ id = ctx->groups[R600_GROUP_CONFIG].offset_block_id[offset >> 2];
+ block = &ctx->groups[R600_GROUP_CONFIG].blocks[id];
+ block->pm4[0] = state->regs[3].value;
+ block->pm4[1] = state->regs[4].value;
+ block->pm4[2] = state->regs[5].value;
+ block->pm4[3] = state->regs[6].value;
+ block->status |= R600_BLOCK_STATUS_ENABLED;
+ block->status |= R600_BLOCK_STATUS_DIRTY;
+ ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+}
+
+void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+ unsigned offset;
+
+ offset = 0x0003C000 + id * 0xc;
+ r600_context_pipe_state_set_sampler(ctx, state, offset);
+ if (state->nregs > 3) {
+ offset = 0x0000A400 + id * 0x10;
+ r600_context_pipe_state_set_sampler_border(ctx, state, offset);
+ }
+}
+
+void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
+{
+ unsigned offset;
+
+ offset = 0x0003C0D8 + id * 0xc;
+ r600_context_pipe_state_set_sampler(ctx, state, offset);
+ if (state->nregs > 3) {
+ offset = 0x0000A600 + id * 0x10;
+ r600_context_pipe_state_set_sampler_border(ctx, state, offset);
+ }
+}
+
+static inline void r600_context_group_emit_dirty(struct r600_context *ctx, struct r600_group *group, unsigned opcode)
+{
+ for (int i = 0; i < group->nblocks; i++) {
+ struct r600_group_block *block = &group->blocks[i];
+ if (block->status & R600_BLOCK_STATUS_DIRTY) {
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(opcode, block->nreg);
+ ctx->pm4[ctx->pm4_cdwords++] = (block->start_offset - group->start_offset) >> 2;
+ memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, block->pm4_ndwords * 4);
+ ctx->pm4_cdwords += block->pm4_ndwords;
+ block->status ^= R600_BLOCK_STATUS_DIRTY;
+ }
+ }
+}
+
+void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
+{
+ unsigned ndwords = 9;
+
+ if (draw->indices) {
+ ndwords = 13;
+ /* make sure there is enough relocation space before scheduling draw */
+ if (ctx->creloc >= (ctx->nreloc - 1)) {
+ r600_context_flush(ctx);
+ }
+ }
+ if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) {
+ /* need to flush */
+ r600_context_flush(ctx);
+ }
+ /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */
+ if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) {
+ R600_ERR("context is too big to be scheduled\n");
+ return;
+ }
+ /* Ok we enough room to copy packet */
+ r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_CONFIG], PKT3_SET_CONFIG_REG);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_CONTEXT], PKT3_SET_CONTEXT_REG);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_ALU_CONST], PKT3_SET_ALU_CONST);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_SAMPLER], PKT3_SET_SAMPLER);
+ r600_context_group_emit_dirty(ctx, &ctx->groups[R600_GROUP_RESOURCE], PKT3_SET_RESOURCE);
+ /* draw packet */
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_INDEX_TYPE, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_index_type;
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NUM_INSTANCES, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_instances;
+ if (draw->indices) {
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX, 3);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->indices_bo_offset;
+ ctx->pm4[ctx->pm4_cdwords++] = 0;
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = 0;
+ r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], draw->indices);
+ } else {
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_num_indices;
+ ctx->pm4[ctx->pm4_cdwords++] = draw->vgt_draw_initiator;
+ }
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0);
+ ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+}
+
+void r600_context_flush(struct r600_context *ctx)
+{
+ struct drm_radeon_cs drmib;
+ struct drm_radeon_cs_chunk chunks[2];
+ uint64_t chunk_array[2];
+ struct r600_group_block *block;
+ int r;
+
+ if (!ctx->pm4_cdwords)
+ return;
+
+#if 1
+ /* emit cs */
+ drmib.num_chunks = 2;
+ drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
+ chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
+ chunks[0].length_dw = ctx->pm4_cdwords;
+ chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
+ chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
+ chunks[1].length_dw = ctx->creloc * sizeof(struct r600_reloc) / 4;
+ chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
+ chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
+ chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
+ r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
+ sizeof(struct drm_radeon_cs));
+#endif
+ /* restart */
+ for (int i = 0; i < ctx->creloc; i++) {
+ radeon_ws_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
+ }
+ ctx->creloc = 0;
+ ctx->pm4_dirty_cdwords = 0;
+ ctx->pm4_cdwords = 0;
+ for (int i = 0; i < ctx->ngroups; i++) {
+ for (int j = 0; j < ctx->groups[i].nblocks; j++) {
+ /* mark enabled block as dirty */
+ block = &ctx->groups[i].blocks[j];
+ if (block->status & R600_BLOCK_STATUS_ENABLED) {
+ ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords;
+ block->status |= R600_BLOCK_STATUS_DIRTY;
+ for (int k = 1; k <= block->nbo; k++) {
+ for (int l = 0; l < block->reloc[k].nreloc; l++) {
+ r600_context_bo_reloc(ctx,
+ &block->pm4[block->reloc[k].bo_pm4_index[l]],
+ block->reloc[k].bo);
+ }
+ }
+ }
+ }
+ }
+}
+
+void r600_context_dump_bof(struct r600_context *ctx, const char *file)
+{
+ bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
+ unsigned i;
+
+ root = device_id = bcs = blob = array = bo = size = handle = NULL;
+ root = bof_object();
+ if (root == NULL)
+ goto out_err;
+ device_id = bof_int32(ctx->radeon->device);
+ if (device_id == NULL)
+ return;
+ if (bof_object_set(root, "device_id", device_id))
+ goto out_err;
+ bof_decref(device_id);
+ device_id = NULL;
+ /* dump relocs */
+ blob = bof_blob(ctx->creloc * 16, ctx->reloc);
+ if (blob == NULL)
+ goto out_err;
+ if (bof_object_set(root, "reloc", blob))
+ goto out_err;
+ bof_decref(blob);
+ blob = NULL;
+ /* dump cs */
+ blob = bof_blob(ctx->pm4_cdwords * 4, ctx->pm4);
+ if (blob == NULL)
+ goto out_err;
+ if (bof_object_set(root, "pm4", blob))
+ goto out_err;
+ bof_decref(blob);
+ blob = NULL;
+ /* dump bo */
+ array = bof_array();
+ if (array == NULL)
+ goto out_err;
+ for (i = 0; i < ctx->creloc; i++) {
+ struct radeon_bo *rbo = radeon_bo_pb_get_bo(ctx->bo[i]->pb);
+ bo = bof_object();
+ if (bo == NULL)
+ goto out_err;
+ size = bof_int32(rbo->size);
+ if (size == NULL)
+ goto out_err;
+ if (bof_object_set(bo, "size", size))
+ goto out_err;
+ bof_decref(size);
+ size = NULL;
+ handle = bof_int32(rbo->handle);
+ if (handle == NULL)
+ goto out_err;
+ if (bof_object_set(bo, "handle", handle))
+ goto out_err;
+ bof_decref(handle);
+ handle = NULL;
+ radeon_bo_map(ctx->radeon, rbo);
+ blob = bof_blob(rbo->size, rbo->data);
+ radeon_bo_unmap(ctx->radeon, rbo);
+ if (blob == NULL)
+ goto out_err;
+ if (bof_object_set(bo, "data", blob))
+ goto out_err;
+ bof_decref(blob);
+ blob = NULL;
+ if (bof_array_append(array, bo))
+ goto out_err;
+ bof_decref(bo);
+ bo = NULL;
+ }
+ if (bof_object_set(root, "bo", array))
+ goto out_err;
+ bof_dump_file(root, file);
+out_err:
+ bof_decref(blob);
+ bof_decref(array);
+ bof_decref(bo);
+ bof_decref(size);
+ bof_decref(handle);
+ bof_decref(device_id);
+ bof_decref(root);
+}
#ifndef R600D_H
#define R600D_H
+/* evergreen values */
+#define EG_RESOURCE_OFFSET 0x00030000
+#define EG_RESOURCE_END 0x00030400
+#define EG_LOOP_CONST_OFFSET 0x0003A200
+#define EG_LOOP_CONST_END 0x0003A26C
+#define EG_BOOL_CONST_OFFSET 0x0003A500
+#define EG_BOOL_CONST_END 0x0003A506
+
+
#define R600_CONFIG_REG_OFFSET 0X00008000
#define R600_CONFIG_REG_END 0X0000AC00
#define R600_CONTEXT_REG_OFFSET 0X00028000
#define R600_BOOL_CONST_OFFSET 0X0003E380
#define R600_BOOL_CONST_END 0X00040000
-/* evergreen values */
-#define EG_RESOURCE_OFFSET 0x00030000
-#define EG_RESOURCE_END 0x00030400
-#define EG_LOOP_CONST_OFFSET 0x0003A200
-#define EG_LOOP_CONST_END 0x0003A26C
-#define EG_BOOL_CONST_OFFSET 0x0003A500
-#define EG_BOOL_CONST_END 0x0003A506
-
-
#define PKT3_NOP 0x10
#define PKT3_INDIRECT_BUFFER_END 0x17
#define PKT3_SET_PREDICATION 0x20
#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
#define C_028080_SLICE_MAX 0xFF001FFF
+#define R_028084_CB_COLOR1_VIEW 0x028084
+#define R_028088_CB_COLOR2_VIEW 0x028088
+#define R_02808C_CB_COLOR3_VIEW 0x02808C
+#define R_028090_CB_COLOR4_VIEW 0x028090
+#define R_028094_CB_COLOR5_VIEW 0x028094
+#define R_028098_CB_COLOR6_VIEW 0x028098
+#define R_02809C_CB_COLOR7_VIEW 0x02809C
#define R_028100_CB_COLOR0_MASK 0x028100
#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
#define C_028100_FMASK_TILE_MAX 0x00000FFF
+#define R_028104_CB_COLOR1_MASK 0x028104
+#define R_028108_CB_COLOR2_MASK 0x028108
+#define R_02810C_CB_COLOR3_MASK 0x02810C
+#define R_028110_CB_COLOR4_MASK 0x028110
+#define R_028114_CB_COLOR5_MASK 0x028114
+#define R_028118_CB_COLOR6_MASK 0x028118
+#define R_02811C_CB_COLOR7_MASK 0x02811C
#define R_028040_CB_COLOR0_BASE 0x028040
#define S_028040_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
#define G_028040_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
#define C_0280E0_BASE_256B 0x00000000
+#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
+#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
+#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
+#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
+#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
+#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
+#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
#define R_0280C0_CB_COLOR0_TILE 0x0280C0
#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
#define C_0280C0_BASE_256B 0x00000000
+#define R_0280C4_CB_COLOR1_TILE 0x0280C4
+#define R_0280C8_CB_COLOR2_TILE 0x0280C8
+#define R_0280CC_CB_COLOR3_TILE 0x0280CC
+#define R_0280D0_CB_COLOR4_TILE 0x0280D0
+#define R_0280D4_CB_COLOR5_TILE 0x0280D4
+#define R_0280D8_CB_COLOR6_TILE 0x0280D8
+#define R_0280DC_CB_COLOR7_TILE 0x0280DC
#define R_028808_CB_COLOR_CONTROL 0x028808
#define S_028808_FOG_ENABLE(x) (((x) & 0x1) << 0)
#define G_028808_FOG_ENABLE(x) (((x) >> 0) & 0x1)
#define C_03000C_W 0x00000000
#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4
#define R_0287E8_VGT_DMA_BASE 0x0287E8
+#define R_028E20_PA_CL_UCP0_X 0x028E20
+#define R_028E24_PA_CL_UCP0_Y 0x028E24
+#define R_028E28_PA_CL_UCP0_Z 0x028E28
+#define R_028E2C_PA_CL_UCP0_W 0x028E2C
+#define R_028E30_PA_CL_UCP1_X 0x028E30
+#define R_028E34_PA_CL_UCP1_Y 0x028E34
+#define R_028E38_PA_CL_UCP1_Z 0x028E38
+#define R_028E3C_PA_CL_UCP1_W 0x028E3C
+#define R_028E40_PA_CL_UCP2_X 0x028E40
+#define R_028E44_PA_CL_UCP2_Y 0x028E44
+#define R_028E48_PA_CL_UCP2_Z 0x028E48
+#define R_028E4C_PA_CL_UCP2_W 0x028E4C
+#define R_028E50_PA_CL_UCP3_X 0x028E50
+#define R_028E54_PA_CL_UCP3_Y 0x028E54
+#define R_028E58_PA_CL_UCP3_Z 0x028E58
+#define R_028E5C_PA_CL_UCP3_W 0x028E5C
+#define R_028E60_PA_CL_UCP4_X 0x028E60
+#define R_028E64_PA_CL_UCP4_Y 0x028E64
+#define R_028E68_PA_CL_UCP4_Z 0x028E68
+#define R_028E6C_PA_CL_UCP4_W 0x028E6C
+#define R_028E70_PA_CL_UCP5_X 0x028E70
+#define R_028E74_PA_CL_UCP5_Y 0x028E74
+#define R_028E78_PA_CL_UCP5_Z 0x028E78
+#define R_028E7C_PA_CL_UCP5_W 0x028E7C
+#define R_038000_RESOURCE0_WORD0 0x038000
+#define R_038004_RESOURCE0_WORD1 0x038004
+#define R_038008_RESOURCE0_WORD2 0x038008
+#define R_03800C_RESOURCE0_WORD3 0x03800C
+#define R_038010_RESOURCE0_WORD4 0x038010
+#define R_038014_RESOURCE0_WORD5 0x038014
+#define R_038018_RESOURCE0_WORD6 0x038018
#endif
projects / mesa.git / commitdiff