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diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index bba4610807b8d70262d739de62d9fcc16291ad41..726db6904adf046a0a4e81bc6d4f5471f338627e 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -101,12 +101,14 @@ Comparative Basic Design Principle:
   guaranteeing binary interoperability)
 * Intel AVX-512 (and below): Hybrid Packed-Predicated SIMD with no
   instruction-overloading, guaranteeing binary interoperability
-  but penalising the ISA with uncontrolled opcode proliferation.
+  but at the same time penalising the ISA with runaway
+  opcode proliferation.
 * ARM SVE/SVE2: Hybrid Packed-Predicated SIMD with instruction-overloading
   that destroys binary interoperability. This is hidden behind the
-  misuse of the word "Scalable".
+  misuse of the word "Scalable" and is **permitted under License**
+  by "Silicon Partners".
 * RISC-V RVV: Cray-style Scalable Vector but with instruction-overloading
-  that destroys binary interoperability.
+  **permitted by the specification** that destroys binary interoperability.
 * SVP64: Cray-style Scalable Vector with no instruction-overloaded
   meanings.  The regfile numbers and bitwidths shall **not** change
   in a future revision (for the same instruction encoding):