build/xilinx: cleanup Vivado/ISE special_overrides

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index 2fdb9454a507331a0be23520cd3b0e5f1f3e3ed1..2f069e6a3a80bab36e0922435ffe282e79ad3e4b 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -42,27 +42,52 @@ def settings(path, ver=None, sub=None):
     raise OSError("no settings file found")
 
 
-class XilinxNoRetimingImpl(Module):
+class XilinxNoRetimingVivadoImpl(Module):
     def __init__(self, reg):
-        reg.attribute += " OPTIMIZE =\"OFF\"," # XXX "register balancing is no" equivalent?
+        pass # No equivalent in Vivado
 
 
-class XilinxNoRetiming:
+class XilinxNoRetimingVivado:
     @staticmethod
     def lower(dr):
-        return XilinxNoRetimingImpl(dr.reg)
+        return XilinxNoRetimingVivadoImpl(dr.reg)
 
-class XilinxMultiRegImpl(MultiRegImpl):
+
+class XilinxNoRetimingISEImpl(Module):
+    def __init__(self, reg):
+        self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
+
+
+class XilinxNoRetimingISE:
+    @staticmethod
+    def lower(dr):
+        return XilinxNoRetimingISEImpl(dr.reg)
+
+
+class XilinxMultiRegVivadoImpl(MultiRegImpl):
     def __init__(self, *args, **kwargs):
         MultiRegImpl.__init__(self, *args, **kwargs)
         for reg in self.regs:
             reg.attribute += " SHIFT_EXTRACT=\"NO\", ASYNC_REG=\"TRUE\","
 
 
-class XilinxMultiReg:
+class XilinxMultiRegVivado:
+    @staticmethod
+    def lower(dr):
+        return XilinxMultiRegVivadoImpl(dr.i, dr.o, dr.odomain, dr.n)
+
+
+class XilinxMultiRegISEImpl(MultiRegImpl):
+    def __init__(self, *args, **kwargs):
+        MultiRegImpl.__init__(self, *args, **kwargs)
+        self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
+            for r in self.regs]
+
+
+class XilinxMultiRegISE:
     @staticmethod
     def lower(dr):
-        return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
+        return XilinxMultiRegISEImpl(dr.i, dr.o, dr.odomain, dr.n)
 
 
 class XilinxAsyncResetSynchronizerImpl(Module):
@@ -120,8 +145,6 @@ class XilinxDDROutput:
 
 
 xilinx_special_overrides = {
-    NoRetiming:             XilinxNoRetiming,
-    MultiReg:               XilinxMultiReg,
     AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
     DifferentialInput:      XilinxDifferentialInput,
     DifferentialOutput:     XilinxDifferentialOutput,
@@ -129,6 +152,18 @@ xilinx_special_overrides = {
 }
 
 
+xilinx_vivado_special_overrides = {
+    NoRetiming:             XilinxNoRetimingVivado,
+    MultiReg:               XilinxMultiRegVivado
+}
+
+
+xilinx_ise_special_overrides = {
+    NoRetiming:             XilinxNoRetimingISE,
+    MultiReg:               XilinxMultiRegISE
+}
+
+
 class XilinxDDROutputImplS7(Module):
     def __init__(self, i1, i2, o, clk):
         self.specials += Instance("ODDR",

diff --git a/litex/build/xilinx/platform.py b/litex/build/xilinx/platform.py
index 3be64f286460c1a51787d39e08daa1a252a0e744..b26678100b367f74404cba9f9b0a0dbd6c31c000 100644 (file)
--- a/litex/build/xilinx/platform.py
+++ b/litex/build/xilinx/platform.py
@@ -18,6 +18,10 @@ class XilinxPlatform(GenericPlatform):
         so = dict(common.xilinx_special_overrides)
         if self.device[:3] == "xc7":
             so.update(common.xilinx_s7_special_overrides)
+        if self.toolchain == "ise":
+            so.update(common.xilinx_vivado_special_overrides)
+        else:
+            so.update(common.xilinx_ise_special_overrides)
         so.update(special_overrides)
         return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)