{
ppir_alu_node *alu = ppir_node_to_alu(node);
- ppir_node *move = ppir_node_create(block, ppir_op_mov, -1, 0);
+ ppir_node *move = ppir_node_create(block, ppir_op_sel_cond, -1, 0);
if (!move)
return false;
list_addtail(&move->list, &node->list);
move_alu->num_src = 1;
ppir_dest *move_dest = &move_alu->dest;
- move_dest->type = ppir_target_ssa;
- move_dest->ssa.num_components = 1;
- move_dest->ssa.live_in = INT_MAX;
- move_dest->ssa.live_out = 0;
+ move_dest->type = ppir_target_pipeline;
+ move_dest->pipeline = ppir_pipeline_reg_fmul;
move_dest->write_mask = 1;
ppir_node_foreach_pred(node, dep) {
PPIR_INSTR_SLOT_END
},
},
+ [ppir_op_sel_cond] = {
+ /* effectively mov, but must be scheduled only to
+ * PPIR_INSTR_SLOT_ALU_SCL_MUL */
+ .name = "sel_cond",
+ .slots = (int []) {
+ PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_END
+ },
+ },
[ppir_op_select] = {
.name = "select",
.slots = (int []) {
ppir_node *succ = ppir_node_first_succ(node);
if (succ->instr_pos == PPIR_INSTR_SLOT_ALU_VEC_ADD) {
node->instr_pos = PPIR_INSTR_SLOT_ALU_VEC_MUL;
- /* select instr's condition must be inserted to fmul slot */
- if (succ->op == ppir_op_select &&
- ppir_node_first_pred(succ) == node) {
- assert(alu->dest.ssa.num_components == 1);
- node->instr_pos = PPIR_INSTR_SLOT_ALU_SCL_MUL;
- }
ppir_instr_insert_mul_node(succ, node);
}
else if (succ->instr_pos == PPIR_INSTR_SLOT_ALU_SCL_ADD &&