sdram: define MT46V32M16 and use it on m1/mixxeo

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 10a69eecae506d2c7f76f1465a37448c9ead896c..773b64505aa5682715e8a3ac5f9b17b1df30f78a 100644 (file)
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -62,6 +62,22 @@ class MT48LC4M16(SDRAMModule):
                SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
 
 # DDR
+class MT46V32M16(SDRAMModule):
+       geom_settings = {
+               "nbanks":       4,
+               "nrows":        8192,
+               "ncols":        1024
+       }
+       timing_settings = {
+               "tRP":          15,
+               "tRCD":         15,
+               "tWR":          15,
+               "tWTR":         2,
+               "tREFI":        7800,
+               "tRFC":         70
+       }
+       def __init__(self, clk_freq):
+               SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
 
 # LPDDR
 

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 54943497b7ea36a7063388b4eda58ec800431202..ddd243800b6128574a02d167b4369e132d889b90 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -6,6 +6,7 @@ from mibuild.generic_platform import ConstraintError
 
 from misoclib.others import mxcrg
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT46V32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import norflash16
 from misoclib.cpu.peripherals import gpio
@@ -41,19 +42,7 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
                if not self.with_main_ram:
-                       sdram_geom_settings = sdram.GeomSettings(
-                               bank_a=2,
-                               row_a=13,
-                               col_a=10
-                       )
-                       sdram_timing_settings = sdram.TimingSettings(
-                               tRP=self.ns(15),
-                               tRCD=self.ns(15),
-                               tWR=self.ns(15),
-                               tWTR=2,
-                               tREFI=self.ns(7800, False),
-                               tRFC=self.ns(70),
-                       )
+                       sdram_module = MT46V32M16(self.clk_freq)
                        sdram_controller_settings =  sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
@@ -61,7 +50,7 @@ class BaseSoC(SDRAMSoC):
                        )
                        self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
                                rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
-                       self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+                       self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
                                sdram_controller_settings)