hdl.dsl: add Default(), an alias for Case() with no arguments.

Fixes #197.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 7f85f2d5b476786820384f59dbba8110ef472dc9..5b7aae93615140b2a263cbf1048a896193acd89d 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -289,6 +289,9 @@ class Module(_ModuleBuilderRoot, Elaboratable):
             self._ctrl_context = "Switch"
             self._statements = _outer_case
 
+    def Default(self):
+        return self.Case()
+
     @contextmanager
     def FSM(self, reset=None, domain="sync", name="fsm"):
         self._check_context("FSM", context=None)

diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 02433d858d57d77e2bfe49d90db0314741b22d64..5a579884cb4f069fa1ec155c553f3561ed8a4da8 100644 (file)
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -307,7 +307,7 @@ class DSLTestCase(FHDLTestCase):
         )
         """)
 
-    def test_Switch_default(self):
+    def test_Switch_default_Case(self):
         m = Module()
         with m.Switch(self.w1):
             with m.Case(3):
@@ -324,6 +324,23 @@ class DSLTestCase(FHDLTestCase):
         )
         """)
 
+    def test_Switch_default_Default(self):
+        m = Module()
+        with m.Switch(self.w1):
+            with m.Case(3):
+                m.d.comb += self.c1.eq(1)
+            with m.Default():
+                m.d.comb += self.c2.eq(1)
+        m._flush()
+        self.assertRepr(m._statements, """
+        (
+            (switch (sig w1)
+                (case 0011 (eq (sig c1) (const 1'd1)))
+                (default (eq (sig c2) (const 1'd1)))
+            )
+        )
+        """)
+
     def test_Switch_const_test(self):
         m = Module()
         with m.Switch(1):