ac: add has_ls_vgpr_init_bug to ac_gpu_info
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Fri, 23 Aug 2019 06:52:07 +0000 (08:52 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 27 Aug 2019 06:04:47 +0000 (08:04 +0200)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_pipe.h
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_state_draw.c

index b366dc6be19fb04ffa7bdf42fe7a3e8048de7c4f..5fb1e26376a2ed7baa878745ae3d927504ce0fe0 100644 (file)
@@ -488,6 +488,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                                        info->family == CHIP_VEGA10 ||
                                        info->family == CHIP_RAVEN;
 
+       info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
+                                    info->family == CHIP_RAVEN;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)
index ba09f38edb872e7161926da8b37f1eacaef5c374..c850da22d4ec053b1a5f3b1ff79b717bf16d6360 100644 (file)
@@ -162,6 +162,7 @@ struct radeon_info {
        bool                        has_gfx9_scissor_bug;
        bool                        has_tc_compat_zrange_bug;
        bool                        has_msaa_sample_loc_bug;
+       bool                        has_ls_vgpr_init_bug;
 };
 
 bool ac_query_gpu_info(int fd, void *dev_p,
index d3dcab3cccea4f9ea675a110e101fae1c005cb97..fef44836ea2a361182addefdb077d16f6654f135 100644 (file)
@@ -1135,8 +1135,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
 #include "si_debug_options.h"
        }
 
-       sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
-                                       sscreen->info.family == CHIP_RAVEN;
        sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
        sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
 
index 2d0b83fcf333d923b818e8f44cfa561a932d25d9..7acef0cfef4846d1f30770069840a97539f0006c 100644 (file)
@@ -495,7 +495,6 @@ struct si_screen {
        bool                            has_out_of_order_rast;
        bool                            assume_no_z_fights;
        bool                            commutative_blend_add;
-       bool                            has_ls_vgpr_init_bug;
        bool                            dpbb_allowed;
        bool                            dfsm_allowed;
        bool                            llvm_has_working_vgpr_indexing;
index b8609e49fe16cc7541e9c6fdf27147da46af4da0..28003d1bad27a58df73d126acc188af1bbff95b8 100644 (file)
@@ -7406,7 +7406,7 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx,
                        si_init_exec_from_input(ctx, 3, 0);
 
                if (key->vs_prolog.as_ls &&
-                   ctx->screen->has_ls_vgpr_init_bug) {
+                   ctx->screen->info.has_ls_vgpr_init_bug) {
                        /* If there are no HS threads, SPI loads the LS VGPRs
                         * starting at VGPR 0. Shift them back to where they
                         * belong.
index 788697db02eaeb7f81decc7b04bad5c5906d5833..586925ef72776458a096921ea51c37a86793655a 100644 (file)
@@ -1833,7 +1833,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
        }
 
        if (sctx->tes_shader.cso &&
-           sctx->screen->has_ls_vgpr_init_bug) {
+           sctx->screen->info.has_ls_vgpr_init_bug) {
                /* Determine whether the LS VGPR fix should be applied.
                 *
                 * It is only required when num input CPs > num output CPs,