(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 96aa10cdeba1b0c1b66f93cb0fbea73255f1afd0..f8e86a8d2f1ebd6ffa3a1eec3f8123272c44c619 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -58,13 +58,9 @@ a little unusual to consider in an ISA that is designed for Parallel
 Vector Processing. The reason is to have strictly-defined guaranteed
 behaviour*)
 
-In Vertical-First Mode, the `ALL` bit should not be used.  If set,
-behaviour is `UNDEFINED`.  (*The reason is that Vertical-First hints may
-permit multiple elements up to hint length to be executed in parallel,
-however the number is entirely up to implementors.  Attempting to test
-an arbitrary indeterminate number of Conditional tests is impossible
-to define, and efforts to enforce such defined behaviour interfere with
-Vertical-First mode parallel opportunistic behaviour.*)
+In Vertical-First Mode, the `ALL` bit still applies, but to the elements
+that are executed up to the Hint length, in parallel batches. See
+[[sv/setvl]] for the definition of Vertical-First Hint.
 
 In `svstep` mode, srcstep and dststep are incremented, and then
 tested exactly as in  [[sv/svstep]]. When Rc=1 the test results