+2019-08-31 Stafford Horne <shorne@gmail.com>
+
+ * config/or1k/constraints.md (t): New constraint.
+ * config/or1k/or1k.h (GOT_REGS): New register class.
+ * config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint.
+
2019-08-30 Jim Wilson <jimw@sifive.com>
* config/riscv/riscv.c (riscv_option_override): If -msave-restore
; We use:
; c - sibcall registers
; d - double pair base registers (excludes r0, r30 and r31 which overflow)
+; t - got address registers (excludes LR (r9) which is clobbered by set_got)
; I - constant signed 16-bit
; K - constant unsigned 16-bit
; M - constant signed 16-bit shifted left 16-bits (l.movhi)
(define_register_constraint "d" "DOUBLE_REGS"
"Registers which can be used for double reg pairs.")
+(define_register_constraint "t" "GOT_REGS"
+ "Registers which can be used to store the Global Offset Table (GOT) address.")
+
;; Immediates
(define_constraint "I"
"A signed 16-bit immediate in the range -32768 to 32767."
NO_REGS,
SIBCALL_REGS,
DOUBLE_REGS,
+ GOT_REGS,
GENERAL_REGS,
FLAG_REGS,
ALL_REGS,
"NO_REGS", \
"SIBCALL_REGS", \
"DOUBLE_REGS", \
+ "GOT_REGS", \
"GENERAL_REGS", \
"FLAG_REGS", \
"ALL_REGS" }
{ { 0x00000000, 0x00000000 }, \
{ SIBCALL_REGS_MASK, 0 }, \
{ 0x7f7ffffe, 0x00000000 }, \
+ { 0xfffffdff, 0x00000000 }, \
{ 0xffffffff, 0x00000003 }, \
{ 0x00000000, 0x00000004 }, \
{ 0xffffffff, 0x00000007 } \
;; set_got pattern below. This works because the set_got_tmp insn is the
;; first insn in the stream and that it isn't moved during RA.
(define_insn "set_got_tmp"
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=t")
(unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
""
{
;; The insn to initialize the GOT.
(define_insn "set_got"
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=t")
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
(clobber (reg:SI LR_REGNUM))]
""