* v850.igen (LDSR): Accept but ignore a selID parameter.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index a3139feb750d663b736aaada9c8bbffc4bf68ce2..2c3669c3d1348be242fd6ffebed9fd86f2cb09c3 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,7 @@
+2013-05-13  Nick Clifton  <nickc@redhat.com>
+
+       * v850.igen (LDSR): Accept but ignore a selID parameter.
+
 2013-05-10  Freddie Chopin  <freddie_chopin@op.pl>
 
        * configure: Rebuild.

diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index b0f390313d7dd3953850c4b9599bee4c8d78a7fb..c5b41809f690b1dcc7598fc5a36dc0dcc5cf5280 100644 (file)
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -934,13 +934,15 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 
 
 // LDSR
-regID,111111,RRRRR + 0000000000100000:IX:::ldsr
-"ldsr r<reg1>, s<regID>"
+regID,111111,RRRRR + selID,00000100000:IX:::ldsr
+"ldsr r<reg1>, s<regID>":(selID == 0)
+"ldsr r<reg1>, s<regID>, <selID>"
 {
   uint32 sreg = GR[reg1];
   TRACE_ALU_INPUT1 (GR[reg1]);
   
-   if ((idecode_issue == idecode_v850e2_issue
+  /* FIXME: For now we ignore the selID.  */
+  if (   (idecode_issue == idecode_v850e2_issue
        || idecode_issue == idecode_v850e3v5_issue
        || idecode_issue == idecode_v850e2v3_issue)
       && regID < 28)