utils/litex_sim: fix main_ram_size

diff --git a/litex/utils/litex_sim.py b/litex/utils/litex_sim.py
index 3a485a97cbcc166ff4e00104d729a64ef940a1af..808bd8b9bdef9ee44ba720af7478425435794cce 100755 (executable)
--- a/litex/utils/litex_sim.py
+++ b/litex/utils/litex_sim.py
@@ -224,7 +224,7 @@ def main():
     if args.rom_init:
         soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
     if not args.with_sdram:
-        soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB
+        soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
         if args.ram_init is not None:
             soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
     else: