split out instructions from openpower/isa/sprset.mdwn

diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn
index 61454907549ff93c311ee52a8ae1f2a38bd02757..dcea26ffb27cc724d1d8fab8c1708634cdc2ddc4 100644 (file)
--- a/openpower/isa/sprset.mdwn
+++ b/openpower/isa/sprset.mdwn
@@ -27,313 +27,36 @@
 
 <!-- Page 974 -->
 
-# Move To Special Purpose Register
+[[!inline pagenames="openpower/isa/sprset/mtspr" raw="yes"]]
 
-XFX-Form
+[[!inline pagenames="openpower/isa/sprset/mfspr" raw="yes"]]
 
-* mtspr spr,RS
+[[!inline pagenames="openpower/isa/sprset/mcrxrx" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/sprset/mtocrf" raw="yes"]]
 
-    n <- spr
-    switch (n)
-      case(13): see(Book_III_p974)
-      case(808, 809, 810, 811):
-      default:
-        if length(SPR(n)) = 64 then
-          SPR(n) <- (RS)
-        else
-          SPR(n) <- (RS) [32:63]
+[[!inline pagenames="openpower/isa/sprset/mtcrf" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/sprset/mfocrf" raw="yes"]]
 
-    See spec 3.3.17
+[[!inline pagenames="openpower/isa/sprset/mfcr" raw="yes"]]
 
-<!-- Page 975 -->
+[[!inline pagenames="openpower/isa/sprset/setb" raw="yes"]]
 
-# Move From Special Purpose Register
+[[!inline pagenames="openpower/isa/sprset/setbc" raw="yes"]]
 
-XFX-Form
+[[!inline pagenames="openpower/isa/sprset/setbcr" raw="yes"]]
 
-* mfspr RT,spr
+[[!inline pagenames="openpower/isa/sprset/setnbc" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/sprset/setnbcr" raw="yes"]]
 
-    n <- spr
-    switch (n)
-      case(129): see(Book_III_p975)
-      case(808, 809, 810, 811):
-      default:
-        if length(SPR(n)) = 64 then
-          RT <- SPR(n)
-        else
-          RT <- [0]*32 || SPR(n)
+[[!inline pagenames="openpower/isa/sprset/mtmsr" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/sprset/mtmsrd" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/sprset/mfmsr" raw="yes"]]
 
-<!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
-
-# Move to CR from XER Extended
-
-X-Form
-
-* mcrxrx BF
-
-Pseudo-code:
-
-    CR[4*BF+32:4*BF+35] <-  XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
-
-Special Registers Altered:
-
-    CR field BF
-
-# Move To One Condition Register Field
-
-XFX-Form
-
-* mtocrf FXM,RS
-
-Pseudo-code:
-
-    n <- 7
-    do i = 7 to 0
-      if FXM[i] = 1 then
-        n <- i
-    CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
-
-Special Registers Altered:
-
-    CR field selected by FXM
-
-# Move To Condition Register Fields
-
-XFX-Form
-
-* mtcrf FXM,RS
-
-Pseudo-code:
-
-    do n = 0 to 7
-      if FXM[n] = 1 then
-        CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
-
-Special Registers Altered:
-
-    CR fields selected by mask
-
-# Move From One Condition Register Field
-
-XFX-Form
-
-* mfocrf RT,FXM
-
-Pseudo-code:
-
-    done <- 0
-    RT <- [0]*64
-    do n = 0 to 7
-      if (done = 0) & (FXM[n] = 1) then
-        RT[4*n+32:4*n+35] <- CR[4*n+32:4*n+35]
-        done <- 1
-
-Special Registers Altered:
-
-    None
-
-# Move From Condition Register
-
-XFX-Form
-
-* mfcr RT
-
-Pseudo-code:
-
-    RT <- [0]*32 || CR
-
-Special Registers Altered:
-
-    None
-
-# Set Boolean
-
-X-Form
-
-* setb RT,BFA
-
-Pseudo-code:
-
-    if CR[4*BFA+32] = 1 then
-       RT <- 0xFFFF_FFFF_FFFF_FFFF
-    else if CR[4*BFA+33]=1 then
-       RT <- 0x0000_0000_0000_0001
-    else
-       RT <- 0x0000_0000_0000_0000
-
-Special Registers Altered:
-
-    None
-
-# Set Boolean Condition
-
-X-Form
-
-* setbc RT,BI
-
-Pseudo-code:
-
-    RT <- (CR[BI + 32] = 1) ? 1 : 0
-
-Special Registers Altered:
-
-    None
-
-# Set Boolean Condition Reverse
-
-X-Form
-
-* setbcr RT,BI
-
-Pseudo-code:
-
-    RT <- (CR[BI + 32] = 1) ? 0 : 1
-
-Special Registers Altered:
-
-    None
-
-# Set Negative Boolean Condition
-
-X-Form
-
-* setnbc RT,BI
-
-Pseudo-code:
-
-    RT <- (CR[BI + 32] = 1) ? -1 : 0
-
-Special Registers Altered:
-
-    None
-
-# Set Negative Boolean Condition Reverse
-
-X-Form
-
-* setnbcr RT,BI
-
-Pseudo-code:
-
-    RT <- (CR[BI + 32] = 1) ? 0 : -1
-
-Special Registers Altered:
-
-    None
-
-<!-- Out of order from the PDF. Page 977 -->
-
-# Move To Machine State Register
-
-X-Form
-
-* mtmsr RS,L1
-
-Pseudo-code:
-
-    if L1 = 0 then
-        MSR[48] <- (RS)[48] | (RS)[49]
-        MSR[58] <- (RS)[58] | (RS)[49]
-        MSR[59] <- (RS)[59] | (RS)[49]
-        MSR[32:40] <- (RS)[32:40]
-        MSR[42:47] <- (RS)[42:47]
-        MSR[49:50] <- (RS)[49:50]
-        MSR[52:57] <- (RS)[52:57]
-        MSR[60:62] <- (RS)[60:62]
-    else
-        MSR[48] <- (RS)[48]
-        MSR[62] <- (RS)[62]
-
-Special Registers Altered:
-
-    MSR
-
-# Move To Machine State Register
-
-X-Form
-
-* mtmsrd RS,L1
-
-Pseudo-code:
-
-    if L1 = 0 then
-        if (MSR[29:31] != 0b010) | ((RS)[29:31] != 0b000) then
-            MSR[29:31] <- (RS)[29:31]
-        MSR[48] <- (RS)[48] | (RS)[49]
-        MSR[58] <- (RS)[58] | (RS)[49]
-        MSR[59] <- (RS)[59] | (RS)[49]
-        MSR[0:2] <- (RS)[0:2]
-        MSR[4:28] <- (RS)[4:28]
-        MSR[32:40] <- (RS)[32:40]
-        MSR[42:47] <- (RS)[42:47]
-        MSR[49:50] <- (RS)[49:50]
-        MSR[52:57] <- (RS)[52:57]
-        MSR[60:62] <- (RS)[60:62]
-    else
-        MSR[48] <- (RS)[48]
-        MSR[62] <- (RS)[62]
-
-Special Registers Altered:
-
-    MSR
-
-# Move From Machine State Register
-
-X-Form
-
-* mfmsr RT
-
-Pseudo-code:
-
-    RT <- MSR
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 4.3.2 Data Cache Instructions Page 850 -->
-
-# Data Cache Block set to Zero
-
-X-Form
-
-* dcbz RA,RB
-
-Pseudo-code:
-
-    if RA = 0 then b <- 0
-    else           b <-(RA)
-    EA <- b + (RB)
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 5.9.3.3 TLB Management Instructions Page 1033 -->
-
-# TLB Invalidate Entry
-
-X-Form
-
-* tlbie RB,RS,RIC,PRS,R
-
-Pseudo-code:
-
-    IS <- (RB) [52:53]
-
-Special Registers Altered:
-
-    None
+[[!inline pagenames="openpower/isa/sprset/dcbz" raw="yes"]]
 
-<!-- MISSING tlbiel page 1038 -->
-<!-- MISSING tlbsync page 1042 -->
+[[!inline pagenames="openpower/isa/sprset/tlbie" raw="yes"]]

diff --git a/openpower/isa/sprset/dcbz.mdwn b/openpower/isa/sprset/dcbz.mdwn
new file mode 100644 (file)
index 0000000..dbf9826
--- /dev/null
+++ b/openpower/isa/sprset/dcbz.mdwn
@@ -0,0 +1,15 @@
+# Data Cache Block set to Zero
+
+X-Form
+
+* dcbz RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/dcbz_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 5.9.3.3 TLB Management Instructions Page 1033 -->

diff --git a/openpower/isa/sprset/dcbz_code.mdwn b/openpower/isa/sprset/dcbz_code.mdwn
new file mode 100644 (file)
index 0000000..4611425
--- /dev/null
+++ b/openpower/isa/sprset/dcbz_code.mdwn
@@ -0,0 +1,3 @@
+    if RA = 0 then b <- 0
+    else           b <-(RA)
+    EA <- b + (RB)

diff --git a/openpower/isa/sprset/mcrxrx.mdwn b/openpower/isa/sprset/mcrxrx.mdwn
new file mode 100644 (file)
index 0000000..54c7768
--- /dev/null
+++ b/openpower/isa/sprset/mcrxrx.mdwn
@@ -0,0 +1,13 @@
+# Move to CR from XER Extended
+
+X-Form
+
+* mcrxrx BF
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mcrxrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR field BF

diff --git a/openpower/isa/sprset/mcrxrx_code.mdwn b/openpower/isa/sprset/mcrxrx_code.mdwn
new file mode 100644 (file)
index 0000000..f100b48
--- /dev/null
+++ b/openpower/isa/sprset/mcrxrx_code.mdwn
@@ -0,0 +1 @@
+    CR[4*BF+32:4*BF+35] <-  XER[OV] || XER[OV32] || XER[CA] || XER[CA32]

diff --git a/openpower/isa/sprset/mfcr.mdwn b/openpower/isa/sprset/mfcr.mdwn
new file mode 100644 (file)
index 0000000..0fefccb
--- /dev/null
+++ b/openpower/isa/sprset/mfcr.mdwn
@@ -0,0 +1,13 @@
+# Move From Condition Register
+
+XFX-Form
+
+* mfcr RT
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mfcr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/sprset/mfcr_code.mdwn b/openpower/isa/sprset/mfcr_code.mdwn
new file mode 100644 (file)
index 0000000..e44e65b
--- /dev/null
+++ b/openpower/isa/sprset/mfcr_code.mdwn
@@ -0,0 +1 @@
+    RT <- [0]*32 || CR

diff --git a/openpower/isa/sprset/mfmsr.mdwn b/openpower/isa/sprset/mfmsr.mdwn
new file mode 100644 (file)
index 0000000..a096c10
--- /dev/null
+++ b/openpower/isa/sprset/mfmsr.mdwn
@@ -0,0 +1,15 @@
+# Move From Machine State Register
+
+X-Form
+
+* mfmsr RT
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mfmsr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 4.3.2 Data Cache Instructions Page 850 -->

diff --git a/openpower/isa/sprset/mfmsr_code.mdwn b/openpower/isa/sprset/mfmsr_code.mdwn
new file mode 100644 (file)
index 0000000..f41489e
--- /dev/null
+++ b/openpower/isa/sprset/mfmsr_code.mdwn
@@ -0,0 +1 @@
+    RT <- MSR

diff --git a/openpower/isa/sprset/mfocrf.mdwn b/openpower/isa/sprset/mfocrf.mdwn
new file mode 100644 (file)
index 0000000..7ec9606
--- /dev/null
+++ b/openpower/isa/sprset/mfocrf.mdwn
@@ -0,0 +1,13 @@
+# Move From One Condition Register Field
+
+XFX-Form
+
+* mfocrf RT,FXM
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mfocrf_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/sprset/mfocrf_code.mdwn b/openpower/isa/sprset/mfocrf_code.mdwn
new file mode 100644 (file)
index 0000000..5104087
--- /dev/null
+++ b/openpower/isa/sprset/mfocrf_code.mdwn
@@ -0,0 +1,6 @@
+    done <- 0
+    RT <- [0]*64
+    do n = 0 to 7
+      if (done = 0) & (FXM[n] = 1) then
+        RT[4*n+32:4*n+35] <- CR[4*n+32:4*n+35]
+        done <- 1

diff --git a/openpower/isa/sprset/mfspr.mdwn b/openpower/isa/sprset/mfspr.mdwn
new file mode 100644 (file)
index 0000000..55198f6
--- /dev/null
+++ b/openpower/isa/sprset/mfspr.mdwn
@@ -0,0 +1,15 @@
+# Move From Special Purpose Register
+
+XFX-Form
+
+* mfspr RT,spr
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mfspr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->

diff --git a/openpower/isa/sprset/mfspr_code.mdwn b/openpower/isa/sprset/mfspr_code.mdwn
new file mode 100644 (file)
index 0000000..f9c2c01
--- /dev/null
+++ b/openpower/isa/sprset/mfspr_code.mdwn
@@ -0,0 +1,9 @@
+    n <- spr
+    switch (n)
+      case(129): see(Book_III_p975)
+      case(808, 809, 810, 811):
+      default:
+        if length(SPR(n)) = 64 then
+          RT <- SPR(n)
+        else
+          RT <- [0]*32 || SPR(n)

diff --git a/openpower/isa/sprset/mtcrf.mdwn b/openpower/isa/sprset/mtcrf.mdwn
new file mode 100644 (file)
index 0000000..5689ef3
--- /dev/null
+++ b/openpower/isa/sprset/mtcrf.mdwn
@@ -0,0 +1,13 @@
+# Move To Condition Register Fields
+
+XFX-Form
+
+* mtcrf FXM,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mtcrf_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR fields selected by mask

diff --git a/openpower/isa/sprset/mtcrf_code.mdwn b/openpower/isa/sprset/mtcrf_code.mdwn
new file mode 100644 (file)
index 0000000..9e33b38
--- /dev/null
+++ b/openpower/isa/sprset/mtcrf_code.mdwn
@@ -0,0 +1,3 @@
+    do n = 0 to 7
+      if FXM[n] = 1 then
+        CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]

diff --git a/openpower/isa/sprset/mtmsr.mdwn b/openpower/isa/sprset/mtmsr.mdwn
new file mode 100644 (file)
index 0000000..8da42cc
--- /dev/null
+++ b/openpower/isa/sprset/mtmsr.mdwn
@@ -0,0 +1,13 @@
+# Move To Machine State Register
+
+X-Form
+
+* mtmsr RS,L1
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mtmsr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    MSR

diff --git a/openpower/isa/sprset/mtmsr_code.mdwn b/openpower/isa/sprset/mtmsr_code.mdwn
new file mode 100644 (file)
index 0000000..8518345
--- /dev/null
+++ b/openpower/isa/sprset/mtmsr_code.mdwn
@@ -0,0 +1,12 @@
+    if L1 = 0 then
+        MSR[48] <- (RS)[48] | (RS)[49]
+        MSR[58] <- (RS)[58] | (RS)[49]
+        MSR[59] <- (RS)[59] | (RS)[49]
+        MSR[32:40] <- (RS)[32:40]
+        MSR[42:47] <- (RS)[42:47]
+        MSR[49:50] <- (RS)[49:50]
+        MSR[52:57] <- (RS)[52:57]
+        MSR[60:62] <- (RS)[60:62]
+    else
+        MSR[48] <- (RS)[48]
+        MSR[62] <- (RS)[62]

diff --git a/openpower/isa/sprset/mtmsrd.mdwn b/openpower/isa/sprset/mtmsrd.mdwn
new file mode 100644 (file)
index 0000000..8da44dc
--- /dev/null
+++ b/openpower/isa/sprset/mtmsrd.mdwn
@@ -0,0 +1,13 @@
+# Move To Machine State Register
+
+X-Form
+
+* mtmsrd RS,L1
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mtmsrd_code" raw="yes"]]
+
+Special Registers Altered:
+
+    MSR

diff --git a/openpower/isa/sprset/mtmsrd_code.mdwn b/openpower/isa/sprset/mtmsrd_code.mdwn
new file mode 100644 (file)
index 0000000..e450901
--- /dev/null
+++ b/openpower/isa/sprset/mtmsrd_code.mdwn
@@ -0,0 +1,16 @@
+    if L1 = 0 then
+        if (MSR[29:31] != 0b010) | ((RS)[29:31] != 0b000) then
+            MSR[29:31] <- (RS)[29:31]
+        MSR[48] <- (RS)[48] | (RS)[49]
+        MSR[58] <- (RS)[58] | (RS)[49]
+        MSR[59] <- (RS)[59] | (RS)[49]
+        MSR[0:2] <- (RS)[0:2]
+        MSR[4:28] <- (RS)[4:28]
+        MSR[32:40] <- (RS)[32:40]
+        MSR[42:47] <- (RS)[42:47]
+        MSR[49:50] <- (RS)[49:50]
+        MSR[52:57] <- (RS)[52:57]
+        MSR[60:62] <- (RS)[60:62]
+    else
+        MSR[48] <- (RS)[48]
+        MSR[62] <- (RS)[62]

diff --git a/openpower/isa/sprset/mtocrf.mdwn b/openpower/isa/sprset/mtocrf.mdwn
new file mode 100644 (file)
index 0000000..b0841a2
--- /dev/null
+++ b/openpower/isa/sprset/mtocrf.mdwn
@@ -0,0 +1,13 @@
+# Move To One Condition Register Field
+
+XFX-Form
+
+* mtocrf FXM,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mtocrf_code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR field selected by FXM

diff --git a/openpower/isa/sprset/mtocrf_code.mdwn b/openpower/isa/sprset/mtocrf_code.mdwn
new file mode 100644 (file)
index 0000000..4075b73
--- /dev/null
+++ b/openpower/isa/sprset/mtocrf_code.mdwn
@@ -0,0 +1,5 @@
+    n <- 7
+    do i = 7 to 0
+      if FXM[i] = 1 then
+        n <- i
+    CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]

diff --git a/openpower/isa/sprset/mtspr.mdwn b/openpower/isa/sprset/mtspr.mdwn
new file mode 100644 (file)
index 0000000..2487ce4
--- /dev/null
+++ b/openpower/isa/sprset/mtspr.mdwn
@@ -0,0 +1,15 @@
+# Move To Special Purpose Register
+
+XFX-Form
+
+* mtspr spr,RS
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/mtspr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    See spec 3.3.17
+
+<!-- Page 975 -->

diff --git a/openpower/isa/sprset/mtspr_code.mdwn b/openpower/isa/sprset/mtspr_code.mdwn
new file mode 100644 (file)
index 0000000..bd03537
--- /dev/null
+++ b/openpower/isa/sprset/mtspr_code.mdwn
@@ -0,0 +1,9 @@
+    n <- spr
+    switch (n)
+      case(13): see(Book_III_p974)
+      case(808, 809, 810, 811):
+      default:
+        if length(SPR(n)) = 64 then
+          SPR(n) <- (RS)
+        else
+          SPR(n) <- (RS) [32:63]

diff --git a/openpower/isa/sprset/setb.mdwn b/openpower/isa/sprset/setb.mdwn
new file mode 100644 (file)
index 0000000..0e82925
--- /dev/null
+++ b/openpower/isa/sprset/setb.mdwn
@@ -0,0 +1,13 @@
+# Set Boolean
+
+X-Form
+
+* setb RT,BFA
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/setb_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/sprset/setb_code.mdwn b/openpower/isa/sprset/setb_code.mdwn
new file mode 100644 (file)
index 0000000..c2bc440
--- /dev/null
+++ b/openpower/isa/sprset/setb_code.mdwn
@@ -0,0 +1,6 @@
+    if CR[4*BFA+32] = 1 then
+       RT <- 0xFFFF_FFFF_FFFF_FFFF
+    else if CR[4*BFA+33]=1 then
+       RT <- 0x0000_0000_0000_0001
+    else
+       RT <- 0x0000_0000_0000_0000

diff --git a/openpower/isa/sprset/setbc.mdwn b/openpower/isa/sprset/setbc.mdwn
new file mode 100644 (file)
index 0000000..8e0971c
--- /dev/null
+++ b/openpower/isa/sprset/setbc.mdwn
@@ -0,0 +1,13 @@
+# Set Boolean Condition
+
+X-Form
+
+* setbc RT,BI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/setbc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/sprset/setbc_code.mdwn b/openpower/isa/sprset/setbc_code.mdwn
new file mode 100644 (file)
index 0000000..b4e3b6f
--- /dev/null
+++ b/openpower/isa/sprset/setbc_code.mdwn
@@ -0,0 +1 @@
+    RT <- (CR[BI + 32] = 1) ? 1 : 0

diff --git a/openpower/isa/sprset/setbcr.mdwn b/openpower/isa/sprset/setbcr.mdwn
new file mode 100644 (file)
index 0000000..c2eddcd
--- /dev/null
+++ b/openpower/isa/sprset/setbcr.mdwn
@@ -0,0 +1,13 @@
+# Set Boolean Condition Reverse
+
+X-Form
+
+* setbcr RT,BI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/setbcr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/sprset/setbcr_code.mdwn b/openpower/isa/sprset/setbcr_code.mdwn
new file mode 100644 (file)
index 0000000..1cc09f8
--- /dev/null
+++ b/openpower/isa/sprset/setbcr_code.mdwn
@@ -0,0 +1 @@
+    RT <- (CR[BI + 32] = 1) ? 0 : 1

diff --git a/openpower/isa/sprset/setnbc.mdwn b/openpower/isa/sprset/setnbc.mdwn
new file mode 100644 (file)
index 0000000..6474c0a
--- /dev/null
+++ b/openpower/isa/sprset/setnbc.mdwn
@@ -0,0 +1,13 @@
+# Set Negative Boolean Condition
+
+X-Form
+
+* setnbc RT,BI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/setnbc_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/sprset/setnbc_code.mdwn b/openpower/isa/sprset/setnbc_code.mdwn
new file mode 100644 (file)
index 0000000..0a88848
--- /dev/null
+++ b/openpower/isa/sprset/setnbc_code.mdwn
@@ -0,0 +1 @@
+    RT <- (CR[BI + 32] = 1) ? -1 : 0

diff --git a/openpower/isa/sprset/setnbcr.mdwn b/openpower/isa/sprset/setnbcr.mdwn
new file mode 100644 (file)
index 0000000..abe162c
--- /dev/null
+++ b/openpower/isa/sprset/setnbcr.mdwn
@@ -0,0 +1,15 @@
+# Set Negative Boolean Condition Reverse
+
+X-Form
+
+* setnbcr RT,BI
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/setnbcr_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Out of order from the PDF. Page 977 -->

diff --git a/openpower/isa/sprset/setnbcr_code.mdwn b/openpower/isa/sprset/setnbcr_code.mdwn
new file mode 100644 (file)
index 0000000..3c12f35
--- /dev/null
+++ b/openpower/isa/sprset/setnbcr_code.mdwn
@@ -0,0 +1 @@
+    RT <- (CR[BI + 32] = 1) ? 0 : -1

diff --git a/openpower/isa/sprset/tlbie.mdwn b/openpower/isa/sprset/tlbie.mdwn
new file mode 100644 (file)
index 0000000..1b333d2
--- /dev/null
+++ b/openpower/isa/sprset/tlbie.mdwn
@@ -0,0 +1,16 @@
+# TLB Invalidate Entry
+
+X-Form
+
+* tlbie RB,RS,RIC,PRS,R
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/sprset/tlbie_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- MISSING tlbiel page 1038 -->
+<!-- MISSING tlbsync page 1042 -->

diff --git a/openpower/isa/sprset/tlbie_code.mdwn b/openpower/isa/sprset/tlbie_code.mdwn
new file mode 100644 (file)
index 0000000..026a19a
--- /dev/null
+++ b/openpower/isa/sprset/tlbie_code.mdwn
@@ -0,0 +1 @@
+    IS <- (RB) [52:53]