synth_xilinx to call abc with -lut +/xilinx/cells.lut

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index eb37feb83f072cc268d14ef0dcbf4fe5c4f6152b..e2a2dfeeb59c52f57fc37b35a8d21592b41437f4 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,9 +276,9 @@ struct SynthXilinxPass : public Pass
                if (check_label(active, run_from, run_to, "map_luts"))
                {
                        if (abc == "abc9")
-                               Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+                               Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
                        else
-                               Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+                               Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
                        Pass::call(design, "techmap -map +/xilinx/lut_map.v");
                }