{
if (cell->type == "$_NOT_")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
- SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
if (cell->type == "$_AND_")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
- SigBit B = sigmap(cell->getPort("\\B").as_bit());
- SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit B = sigmap(cell->getPort(ID::B).as_bit());
+ SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
if (cell->type == "$initstate")
{
- SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
undriven_bits.erase(Y);
initstate_bits.insert(Y);
continue;
if (cell->type == "$assert")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
if (cell->type == "$assume")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
if (cell->type == "$live")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
if (cell->type == "$fair")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
if (cell->type == "$anyconst")
{
- for (auto bit : sigmap(cell->getPort("\\Y"))) {
+ for (auto bit : sigmap(cell->getPort(ID::Y))) {
undriven_bits.erase(bit);
ff_map[bit] = bit;
}
if (cell->type == "$anyseq")
{
- for (auto bit : sigmap(cell->getPort("\\Y"))) {
+ for (auto bit : sigmap(cell->getPort(ID::Y))) {
undriven_bits.erase(bit);
input_bits.insert(bit);
}
if (!cell->has_keep_attr()) {
if (cell->type == "$_NOT_")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
- SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
if (cell->type == "$_AND_")
{
- SigBit A = sigmap(cell->getPort("\\A").as_bit());
- SigBit B = sigmap(cell->getPort("\\B").as_bit());
- SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit A = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit B = sigmap(cell->getPort(ID::B).as_bit());
+ SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
if (!config->icells_mode && cell->type == "$_NOT_") {
f << stringf(".names %s %s\n0 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_AND_") {
f << stringf(".names %s %s %s\n11 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_OR_") {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_XOR_") {
f << stringf(".names %s %s %s\n10 1\n01 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_NAND_") {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_NOR_") {
f << stringf(".names %s %s %s\n00 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_XNOR_") {
f << stringf(".names %s %s %s\n11 1\n00 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_ANDNOT_") {
f << stringf(".names %s %s %s\n10 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_ORNOT_") {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_AOI3_") {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_OAI3_") {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_AOI4_") {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
- cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
+ cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_OAI4_") {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
- cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
+ cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_MUX_") {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
- cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
+ cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$_NMUX_") {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
- cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
- cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y")));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
+ cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
if (!config->icells_mode && cell->type == "$lut") {
f << stringf(".names");
- auto &inputs = cell->getPort("\\A");
+ auto &inputs = cell->getPort(ID::A);
auto width = cell->parameters.at("\\WIDTH").as_int();
log_assert(inputs.size() == width);
for (int i = width-1; i >= 0; i--)
f << stringf(" %s", cstr(inputs.extract(i, 1)));
- auto &output = cell->getPort("\\Y");
+ auto &output = cell->getPort(ID::Y);
log_assert(output.size() == 1);
f << stringf(" %s", cstr(output));
f << stringf("\n");
if (!config->icells_mode && cell->type == "$sop") {
f << stringf(".names");
- auto &inputs = cell->getPort("\\A");
+ auto &inputs = cell->getPort(ID::A);
auto width = cell->parameters.at("\\WIDTH").as_int();
auto depth = cell->parameters.at("\\DEPTH").as_int();
vector<State> table = cell->parameters.at("\\TABLE").bits;
log_assert(inputs.size() == width);
for (int i = 0; i < width; i++)
f << stringf(" %s", cstr(inputs.extract(i, 1)));
- auto &output = cell->getPort("\\Y");
+ auto &output = cell->getPort(ID::Y);
log_assert(output.size() == 1);
f << stringf(" %s", cstr(output));
f << stringf("\n");
if (top_module_name.empty())
for (auto module : design->modules())
- if (module->get_bool_attribute("\\top"))
+ if (module->get_bool_attribute(ID::top))
top_module_name = module->name.str();
*f << stringf("# Generated by %s\n", yosys_version_str);
if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
log_assert(!btor_op.empty());
- int width = GetSize(cell->getPort("\\Y"));
- width = std::max(width, GetSize(cell->getPort("\\A")));
- width = std::max(width, GetSize(cell->getPort("\\B")));
+ int width = GetSize(cell->getPort(ID::Y));
+ width = std::max(width, GetSize(cell->getPort(ID::A)));
+ width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
if (btor_op == "shift")
{
- int nid_a = get_sig_nid(cell->getPort("\\A"), width, false);
- int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
+ int nid_a = get_sig_nid(cell->getPort(ID::A), width, false);
+ int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_r = next_nid++;
btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);
}
else
{
- int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
- int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
+ int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
+ int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
nid = next_nid++;
btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
}
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
if (cell->type == "$mod") btor_op = "rem";
log_assert(!btor_op.empty());
- int width = GetSize(cell->getPort("\\Y"));
- width = std::max(width, GetSize(cell->getPort("\\A")));
- width = std::max(width, GetSize(cell->getPort("\\B")));
+ int width = GetSize(cell->getPort(ID::Y));
+ width = std::max(width, GetSize(cell->getPort(ID::A)));
+ width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
- int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
- int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
+ int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
+ int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int sid = get_bv_sid(width);
int nid = next_nid++;
btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
{
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
- int nid_b = get_sig_nid(cell->getPort("\\B"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
+ int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid1 = next_nid++;
int nid2 = next_nid++;
btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
add_nid_sig(nid2, sig);
goto okay;
}
if (cell->type.in("$_OAI3_", "$_AOI3_"))
{
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
- int nid_b = get_sig_nid(cell->getPort("\\B"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
+ int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort("\\C"));
int nid1 = next_nid++;
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
}
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
add_nid_sig(nid3, sig);
goto okay;
}
if (cell->type.in("$_OAI4_", "$_AOI4_"))
{
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
- int nid_b = get_sig_nid(cell->getPort("\\B"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
+ int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort("\\C"));
int nid_d = get_sig_nid(cell->getPort("\\D"));
btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
}
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
add_nid_sig(nid4, sig);
goto okay;
}
log_assert(!btor_op.empty());
int width = 1;
- width = std::max(width, GetSize(cell->getPort("\\A")));
- width = std::max(width, GetSize(cell->getPort("\\B")));
+ width = std::max(width, GetSize(cell->getPort(ID::A)));
+ width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
- int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
+ int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
+ int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid = next_nid++;
if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
}
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
if (cell->type == "$neg") btor_op = "neg";
log_assert(!btor_op.empty());
- int width = GetSize(cell->getPort("\\Y"));
- width = std::max(width, GetSize(cell->getPort("\\A")));
+ int width = GetSize(cell->getPort(ID::Y));
+ width = std::max(width, GetSize(cell->getPort(ID::A)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
int sid = get_bv_sid(width);
- int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
+ int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid = next_nid++;
btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
- int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0;
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
+ int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
- if (GetSize(cell->getPort("\\A")) > 1) {
+ if (GetSize(cell->getPort(ID::A)) > 1) {
int nid_red_a = next_nid++;
btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
nid_a = nid_red_a;
}
- if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) {
+ if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
int nid_red_b = next_nid++;
btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
nid_b = nid_red_b;
else
btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid = next_nid++;
btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
}
- SigSpec sig = sigmap(cell->getPort("\\Y"));
+ SigSpec sig = sigmap(cell->getPort(ID::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
if (cell->type.in("$mux", "$_MUX_", "$_NMUX_"))
{
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_s = sigmap(cell->getPort("\\S"));
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_s = sigmap(cell->getPort(ID::S));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
int nid_a = get_sig_nid(sig_a);
int nid_b = get_sig_nid(sig_b);
if (cell->type == "$pmux")
{
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_s = sigmap(cell->getPort("\\S"));
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_s = sigmap(cell->getPort(ID::S));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
int width = GetSize(sig_a);
int sid = get_bv_sid(width);
if (cell->type.in("$anyconst", "$anyseq"))
{
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
if (cell->type == "$initstate")
{
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
if (initstate_nid < 0)
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN"));
int nid_not_en = next_nid++;
int nid_a_or_not_en = next_nid++;
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN"));
int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++;
if (top_module_name.empty())
for (auto module : design->modules())
- if (module->get_bool_attribute("\\top"))
+ if (module->get_bool_attribute(ID::top))
top_module_name = module->name.str();
for (auto module : design->modules())
const char *atLine() {
if (srcLine == "") {
if (pCell) {
- auto p = pCell->attributes.find("\\src");
+ auto p = pCell->attributes.find(ID::src);
srcLine = " at " + p->second.decode_string();
}
}
if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
{
- string a_expr = make_expr(cell->getPort("\\A"));
+ string a_expr = make_expr(cell->getPort(ID::A));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
if (a_signed) {
expr = stringf("asUInt(%s)", expr.c_str());
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
"$logic_and", "$logic_or", "$pow"))
{
- string a_expr = make_expr(cell->getPort("\\A"));
- string b_expr = make_expr(cell->getPort("\\B"));
+ string a_expr = make_expr(cell->getPort(ID::A));
+ string b_expr = make_expr(cell->getPort(ID::B));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
if (a_signed) {
}
// Assume the FIRRTL width is the width of "A"
firrtl_width = a_width;
- auto a_sig = cell->getPort("\\A");
+ auto a_sig = cell->getPort(ID::A);
if (cell->type == "$add") {
primop = "add";
// We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true;
// Is the shift amount constant?
- auto b_sig = cell->getPort("\\B");
+ auto b_sig = cell->getPort(ID::B);
if (b_sig.is_fully_const()) {
primop = "shl";
int shift_amount = b_sig.as_int();
// We don't need to extract a specific range of bits.
extract_y_bits = false;
// Is the shift amount constant?
- auto b_sig = cell->getPort("\\B");
+ auto b_sig = cell->getPort(ID::B);
if (b_sig.is_fully_const()) {
primop = "shr";
int shift_amount = b_sig.as_int();
a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)";
extract_y_bits = true;
// Is the shift amount constant?
- auto b_sig = cell->getPort("\\B");
+ auto b_sig = cell->getPort(ID::B);
if (b_sig.is_fully_const()) {
primop = "shl";
int shiftAmount = b_sig.as_int();
expr = stringf("asUInt(%s)", expr.c_str());
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
if (cell->type.in("$mux"))
{
int width = cell->parameters.at("\\WIDTH").as_int();
- string a_expr = make_expr(cell->getPort("\\A"));
- string b_expr = make_expr(cell->getPort("\\B"));
- string s_expr = make_expr(cell->getPort("\\S"));
+ string a_expr = make_expr(cell->getPort(ID::A));
+ string b_expr = make_expr(cell->getPort(ID::B));
+ string s_expr = make_expr(cell->getPort(ID::S));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), width));
string expr = stringf("mux(%s, %s, %s)", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
// assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop.
- string a_expr = make_expr(cell->getPort("\\A"));
+ string a_expr = make_expr(cell->getPort(ID::A));
// Get the initial bit selector
- string b_expr = make_expr(cell->getPort("\\B"));
+ string b_expr = make_expr(cell->getPort(ID::B));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
if (cell->getParam("\\B_SIGNED").as_bool()) {
string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
if (cell->type == "$shift") {
// assign y = a >> b;
// where b may be negative
- string a_expr = make_expr(cell->getPort("\\A"));
- string b_expr = make_expr(cell->getPort("\\B"));
+ string a_expr = make_expr(cell->getPort(ID::A));
+ string b_expr = make_expr(cell->getPort(ID::B));
auto b_string = b_expr.c_str();
string expr;
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
}
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
if (cell->type == "$pos") {
// assign y = a;
// printCell(cell);
- string a_expr = make_expr(cell->getPort("\\A"));
+ string a_expr = make_expr(cell->getPort(ID::A));
// Verilog appears to treat the result as signed, so if the result is wider than "A",
// we need to pad.
if (a_width < y_width) {
}
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), a_expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
for (auto module : design->modules()) {
make_id(module->name);
last = module;
- if (top == nullptr && module->get_bool_attribute("\\top")) {
+ if (top == nullptr && module->get_bool_attribute(ID::top)) {
top = module;
}
for (auto wire : module->wires())
{
if (cell->type.in("$_BUF_", "$_NOT_"))
{
- SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
- SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
+ SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
+ SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string expr;
if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
{
- SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
- SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
- SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
+ SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
+ SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
+ SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
if (cell->type.in("$_AOI3_", "$_OAI3_"))
{
- SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
- SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
+ SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
+ SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
- SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
+ SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
if (cell->type.in("$_AOI4_", "$_OAI4_"))
{
- SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
- SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
+ SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
+ SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
SigBit d = sigmaps.at(work->module)(cell->getPort("\\D"));
- SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
+ SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
if (cell->type.in("$_MUX_", "$_NMUX_"))
{
- SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
- SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
- SigBit s = sigmaps.at(work->module)(cell->getPort("\\S"));
- SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));
+ SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
+ SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
+ SigBit s = sigmaps.at(work->module)(cell->getPort(ID::S));
+ SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
void export_gate(RTLIL::Cell *cell, std::string expr)
{
- RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
+ RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
std::string processed_expr;
for (char ch : expr) {
- if (ch == 'A') processed_expr += get_bool(cell->getPort("\\A"));
- else if (ch == 'B') processed_expr += get_bool(cell->getPort("\\B"));
+ if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A));
+ else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B));
else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C"));
else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D"));
- else if (ch == 'S') processed_expr += get_bool(cell->getPort("\\S"));
+ else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S));
else processed_expr += ch;
}
void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0)
{
RTLIL::SigSpec sig_a, sig_b;
- RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
int width = GetSize(sig_y);
if (type == 's' || type == 'd' || type == 'b') {
- width = max(width, GetSize(cell->getPort("\\A")));
- if (cell->hasPort("\\B"))
- width = max(width, GetSize(cell->getPort("\\B")));
+ width = max(width, GetSize(cell->getPort(ID::A)));
+ if (cell->hasPort(ID::B))
+ width = max(width, GetSize(cell->getPort(ID::B)));
}
- if (cell->hasPort("\\A")) {
- sig_a = cell->getPort("\\A");
+ if (cell->hasPort(ID::A)) {
+ sig_a = cell->getPort(ID::A);
sig_a.extend_u0(width, is_signed);
}
- if (cell->hasPort("\\B")) {
- sig_b = cell->getPort("\\B");
+ if (cell->hasPort(ID::B)) {
+ sig_b = cell->getPort(ID::B);
sig_b.extend_u0(width, is_signed && !(type == 's'));
}
for (char ch : expr) {
if (ch == 'A') processed_expr += get_bv(sig_a);
else if (ch == 'B') processed_expr += get_bv(sig_b);
- else if (ch == 'P') processed_expr += get_bv(cell->getPort("\\B"));
+ else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B));
else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
else processed_expr += ch;
void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val)
{
- RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
std::string processed_expr;
for (char ch : expr)
if (cell->type == "$initstate")
{
- SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit)));
register_bool(bit, idcounter++);
if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq"))
{
registers.insert(cell);
- string infostr = cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell);
+ string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell);
if (cell->attributes.count("\\reg"))
infostr += " " + cell->attributes.at("\\reg").decode_string();
- decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort("\\Y")), infostr.c_str()));
- if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\maximize")){
+ decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str()));
+ if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\maximize")){
decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
- log("Wire %s is maximized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
+ log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
}
- else if (cell->getPort("\\Y").is_wire() && cell->getPort("\\Y").as_wire()->get_bool_attribute("\\minimize")){
+ else if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\minimize")){
decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
- log("Wire %s is minimized\n", cell->getPort("\\Y").as_wire()->name.str().c_str());
+ log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
}
- makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y")));
+ makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y)));
if (cell->type == "$anyseq")
ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
- register_bv(cell->getPort("\\Y"), idcounter++);
+ register_bv(cell->getPort(ID::Y), idcounter++);
recursive_cells.erase(cell);
return;
}
if (cell->getParam("\\B_SIGNED").as_bool()) {
return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
"(bvlshr A B) (bvlshr A (bvneg B)))",
- GetSize(cell->getPort("\\B")), 0), 's');
+ GetSize(cell->getPort(ID::B)), 0), 's');
} else {
return export_bvop(cell, "(bvlshr A B)", 's');
}
if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd');
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") &&
- 2*GetSize(cell->getPort("\\A").chunks()) < GetSize(cell->getPort("\\A"))) {
+ 2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
bool is_and = cell->type == "$reduce_and";
- string bits(GetSize(cell->getPort("\\A")), is_and ? '1' : '0');
+ string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0');
return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b');
}
if (cell->type.in("$mux", "$pmux"))
{
- int width = GetSize(cell->getPort("\\Y"));
- std::string processed_expr = get_bv(cell->getPort("\\A"));
+ int width = GetSize(cell->getPort(ID::Y));
+ std::string processed_expr = get_bv(cell->getPort(ID::A));
- RTLIL::SigSpec sig_b = cell->getPort("\\B");
- RTLIL::SigSpec sig_s = cell->getPort("\\S");
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
+ RTLIL::SigSpec sig_s = cell->getPort(ID::S);
get_bv(sig_b);
get_bv(sig_s);
if (verbose)
log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell));
- RTLIL::SigSpec sig = sigmap(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y));
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig)));
register_bv(sig, idcounter++);
cell->type == "$assume" ? 'u' :
cell->type == "$cover" ? 'c' : 0;
- string name_a = get_bool(cell->getPort("\\A"));
+ string name_a = get_bool(cell->getPort(ID::A));
string name_en = get_bool(cell->getPort("\\EN"));
- string infostr = (cell->name[0] == '$' && cell->attributes.count("\\src")) ? cell->attributes.at("\\src").decode_string() : get_id(cell);
+ string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell);
decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str()));
if (cell->type == "$cover")
if (cell->type.in("$anyconst", "$allconst"))
{
- std::string expr_d = get_bv(cell->getPort("\\Y"));
- std::string expr_q = get_bv(cell->getPort("\\Y"), "next_state");
- trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Y"))));
+ std::string expr_d = get_bv(cell->getPort(ID::Y));
+ std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state");
+ trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y))));
if (cell->type == "$anyconst")
- ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Y")).c_str(), get_bv(cell->getPort("\\Y"), "other_state").c_str()));
+ ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str()));
}
if (cell->type == "$mem")
if (cell->type.in("$assert"))
{
- SigSpec sig_a = cell->getPort("\\A");
+ SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_en = cell->getPort("\\EN");
invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
{
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_b = cell->getPort("\\B");
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_b = cell->getPort(ID::B);
- int width_y = GetSize(cell->getPort("\\Y"));
+ int width_y = GetSize(cell->getPort(ID::Y));
int shift_b_width = GetSize(sig_b);
int width_ay = max(GetSize(sig_a), width_y);
int width = width_ay;
GetSize(sig_b)-shift_b_width, width_y, expr.c_str());
}
- definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
+ definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str()));
continue;
}
if (cell->type.in("$not", "$pos", "$neg"))
{
- int width = GetSize(cell->getPort("\\Y"));
+ int width = GetSize(cell->getPort(ID::Y));
string expr_a, op;
if (cell->type == "$not") op = "!";
if (cell->getParam("\\A_SIGNED").as_bool())
{
- definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")),
- op.c_str(), rvalue_s(cell->getPort("\\A"), width)));
+ definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
+ op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
}
else
{
- definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")),
- op.c_str(), rvalue_u(cell->getPort("\\A"), width)));
+ definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)),
+ op.c_str(), rvalue_u(cell->getPort(ID::A), width)));
}
continue;
if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor"))
{
- int width = GetSize(cell->getPort("\\Y"));
+ int width = GetSize(cell->getPort(ID::Y));
string expr_a, expr_b, op;
if (cell->type == "$add") op = "+";
if (cell->getParam("\\A_SIGNED").as_bool())
{
- definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")),
- rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width)));
+ definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)),
+ rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width)));
}
else
{
- definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
- rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width)));
+ definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)),
+ rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width)));
}
continue;
if (cell->type.in("$div", "$mod"))
{
- int width_y = GetSize(cell->getPort("\\Y"));
- int width = max(width_y, GetSize(cell->getPort("\\A")));
- width = max(width, GetSize(cell->getPort("\\B")));
+ int width_y = GetSize(cell->getPort(ID::Y));
+ int width = max(width_y, GetSize(cell->getPort(ID::A)));
+ width = max(width, GetSize(cell->getPort(ID::B)));
string expr_a, expr_b, op;
if (cell->type == "$div") op = "/";
if (cell->getParam("\\A_SIGNED").as_bool())
{
- definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
- rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width), width_y));
+ definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
+ rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y));
}
else
{
- definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")),
- rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width), width_y));
+ definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(ID::Y)),
+ rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width), width_y));
}
continue;
if (cell->type.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt"))
{
- int width = max(GetSize(cell->getPort("\\A")), GetSize(cell->getPort("\\B")));
+ int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
string expr_a, expr_b, op;
if (cell->type == "$eq") op = "=";
if (cell->getParam("\\A_SIGNED").as_bool())
{
- expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\A")), width);
- expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort("\\B")), width);
+ expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width);
+ expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width);
}
else
{
- expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort("\\A")), width);
- expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width);
+ expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::A)), width);
+ expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::B)), width);
}
- definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
- expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort("\\Y"))));
+ definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
+ expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(ID::Y))));
continue;
}
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool"))
{
- int width_a = GetSize(cell->getPort("\\A"));
- int width_y = GetSize(cell->getPort("\\Y"));
- const char *expr_a = rvalue(cell->getPort("\\A"));
- const char *expr_y = lvalue(cell->getPort("\\Y"));
+ int width_a = GetSize(cell->getPort(ID::A));
+ int width_y = GetSize(cell->getPort(ID::Y));
+ const char *expr_a = rvalue(cell->getPort(ID::A));
+ const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr;
if (cell->type == "$reduce_and") expr = stringf("%s = !0ub%d_0", expr_a, width_a);
if (cell->type.in("$reduce_xor", "$reduce_xnor"))
{
- int width_y = GetSize(cell->getPort("\\Y"));
- const char *expr_y = lvalue(cell->getPort("\\Y"));
+ int width_y = GetSize(cell->getPort(ID::Y));
+ const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr;
- for (auto bit : cell->getPort("\\A")) {
+ for (auto bit : cell->getPort(ID::A)) {
if (!expr.empty())
expr += " xor ";
expr += rvalue(bit);
if (cell->type.in("$logic_and", "$logic_or"))
{
- int width_a = GetSize(cell->getPort("\\A"));
- int width_b = GetSize(cell->getPort("\\B"));
- int width_y = GetSize(cell->getPort("\\Y"));
+ int width_a = GetSize(cell->getPort(ID::A));
+ int width_b = GetSize(cell->getPort(ID::B));
+ int width_y = GetSize(cell->getPort(ID::Y));
- string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a);
- string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort("\\B")), width_b);
- const char *expr_y = lvalue(cell->getPort("\\Y"));
+ string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a);
+ string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::B)), width_b);
+ const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr;
if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b;
if (cell->type.in("$logic_not"))
{
- int width_a = GetSize(cell->getPort("\\A"));
- int width_y = GetSize(cell->getPort("\\Y"));
+ int width_a = GetSize(cell->getPort(ID::A));
+ int width_y = GetSize(cell->getPort(ID::Y));
- string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a);
- const char *expr_y = lvalue(cell->getPort("\\Y"));
+ string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a);
+ const char *expr_y = lvalue(cell->getPort(ID::Y));
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y));
continue;
if (cell->type.in("$mux", "$pmux"))
{
- int width = GetSize(cell->getPort("\\Y"));
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_b = cell->getPort("\\B");
- SigSpec sig_s = cell->getPort("\\S");
+ int width = GetSize(cell->getPort(ID::Y));
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_b = cell->getPort(ID::B);
+ SigSpec sig_s = cell->getPort(ID::S);
string expr;
for (int i = 0; i < GetSize(sig_s); i++)
expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width)));
expr += rvalue(sig_a);
- definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
+ definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str()));
continue;
}
if (cell->type.in("$_BUF_", "$_NOT_"))
{
string op = cell->type == "$_NOT_" ? "!" : "";
- definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A"))));
+ definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A))));
continue;
}
if (cell->type.in("$_XNOR_")) op = "xnor";
if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
- definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
+ definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
else
if (cell->type.in("$_NAND_", "$_NOR_"))
- definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
+ definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
else
- definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
+ definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
continue;
}
if (cell->type == "$_MUX_")
{
- definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A"))));
+ definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
continue;
}
if (cell->type == "$_NMUX_")
{
- definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A"))));
+ definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
continue;
}
if (cell->type == "$_AOI3_")
{
- definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C"))));
+ definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C"))));
continue;
}
if (cell->type == "$_OAI3_")
{
- definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C"))));
+ definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C"))));
continue;
}
if (cell->type == "$_AOI4_")
{
- definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
+ definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
continue;
}
if (cell->type == "$_OAI4_")
{
- definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")),
- rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
+ definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)),
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
continue;
}
if (top_module_name.empty())
for (auto module : design->modules())
- if (module->get_bool_attribute("\\top"))
+ if (module->get_bool_attribute(ID::top))
top_module_name = module->name.str();
*f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = %s ", op.c_str());
dump_attributes(f, "", cell->attributes, ' ');
dump_cell_expr_port(f, cell, "A", true);
void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" %s ", op.c_str());
{
if (cell->type == "$_NOT_") {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
f << stringf("~");
dump_attributes(f, "", cell->attributes, ' ');
if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_"))
f << stringf("~(");
if (cell->type == "$_MUX_") {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "S", false);
f << stringf(" ? ");
if (cell->type == "$_NMUX_") {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = !(");
dump_cell_expr_port(f, cell, "S", false);
f << stringf(" ? ");
if (cell->type.in("$_AOI3_", "$_OAI3_")) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(cell->type == "$_AOI3_" ? " & " : " | ");
if (cell->type.in("$_AOI4_", "$_OAI4_")) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(cell->type == "$_AOI4_" ? " & " : " | ");
f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort("\\C"));
f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg");
- dump_sigspec(f, cell->getPort("\\S"));
+ dump_sigspec(f, cell->getPort(ID::S));
f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort("\\R"));
f << stringf(")\n");
f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str());
f << stringf("%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!");
- dump_sigspec(f, cell->getPort("\\S"));
+ dump_sigspec(f, cell->getPort(ID::S));
f << stringf(")\n");
f << stringf("%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str());
if (cell->type == "$shift")
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
if (cell->getParam("\\B_SIGNED").as_bool())
{
f << stringf("$signed(");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
f << stringf(")");
f << stringf(" < 0 ? ");
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" << - ");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
f << stringf(" : ");
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" >> ");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
}
else
{
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" >> ");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
}
f << stringf(";\n");
return true;
if (cell->type == "$shiftx")
{
std::string temp_id = next_auto_id();
- f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str());
- dump_sigspec(f, cell->getPort("\\A"));
+ f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str());
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(";\n");
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = %s[", temp_id.c_str());
if (cell->getParam("\\B_SIGNED").as_bool())
f << stringf("$signed(");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
if (cell->getParam("\\B_SIGNED").as_bool())
f << stringf(")");
f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int());
if (cell->type == "$mux")
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
- dump_sigspec(f, cell->getPort("\\S"));
+ dump_sigspec(f, cell->getPort(ID::S));
f << stringf(" ? ");
dump_attributes(f, "", cell->attributes, ' ');
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
f << stringf(" : ");
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(";\n");
return true;
}
if (cell->type == "$pmux")
{
int width = cell->parameters["\\WIDTH"].as_int();
- int s_width = cell->getPort("\\S").size();
+ int s_width = cell->getPort(ID::S).size();
std::string func_name = cellname(cell);
f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
f << stringf("%s" "endfunction\n", indent.c_str());
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = %s(", func_name.c_str());
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(", ");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
f << stringf(", ");
- dump_sigspec(f, cell->getPort("\\S"));
+ dump_sigspec(f, cell->getPort(ID::S));
f << stringf(");\n");
return true;
}
if (cell->type == "$tribuf")
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort("\\EN"));
f << stringf(" ? ");
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
return true;
}
if (cell->type == "$slice")
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
return true;
}
if (cell->type == "$concat")
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = { ");
- dump_sigspec(f, cell->getPort("\\B"));
+ dump_sigspec(f, cell->getPort(ID::B));
f << stringf(" , ");
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" };\n");
return true;
}
if (cell->type == "$lut")
{
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Y"));
+ dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_const(f, cell->parameters.at("\\LUT"));
f << stringf(" >> ");
dump_attributes(f, "", cell->attributes, ' ');
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(";\n");
return true;
}
f << stringf("%s" "always @* if (", indent.c_str());
dump_sigspec(f, cell->getPort("\\EN"));
f << stringf(") %s(", cell->type.c_str()+1);
- dump_sigspec(f, cell->getPort("\\A"));
+ dump_sigspec(f, cell->getPort(ID::A));
f << stringf(");\n");
return true;
}
if (module == nullptr)
log_error("No top module found!\n");
- Wire *wire_a = module->wire("\\A");
- Wire *wire_y = module->wire("\\Y");
+ Wire *wire_a = module->wire(ID::A);
+ Wire *wire_y = module->wire(ID::Y);
if (wire_a == nullptr)
log_error("No wire A found!\n");
sig2deps[output].insert(output);
RTLIL::Cell *cell = sig2driver.at(output);
- RTLIL::SigBit sig_a = cell->getPort("\\A");
+ RTLIL::SigBit sig_a = cell->getPort(ID::A);
sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
compute_deps(sig_a, inputs);
if (cell->type == "$_AND_") {
- RTLIL::SigSpec sig_b = cell->getPort("\\B");
+ RTLIL::SigSpec sig_b = cell->getPort(ID::B);
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
bool eval(RTLIL::Cell *cell)
{
- RTLIL::SigBit sig_y = cell->getPort("\\Y");
+ RTLIL::SigBit sig_y = cell->getPort(ID::Y);
if (values_map.count(sig_y))
return true;
- RTLIL::SigBit sig_a = cell->getPort("\\A");
+ RTLIL::SigBit sig_a = cell->getPort(ID::A);
if (!eval(sig_a))
return false;
}
{
- RTLIL::SigBit sig_b = cell->getPort("\\B");
+ RTLIL::SigBit sig_b = cell->getPort(ID::B);
if (!eval(sig_b))
return false;
if (sig_b == State::S0) {
for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue;
- auto y_port = cell->getPort("\\Y").as_bit();
+ auto y_port = cell->getPort(ID::Y).as_bit();
if (y_port.wire->width == 1)
module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
else
current_module = new AstModule;
current_module->ast = NULL;
current_module->name = ast->str;
- current_module->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
+ current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
ast->location.first_column, ast->location.last_line, ast->location.last_column);
current_module->set_bool_attribute("\\cells_not_processed");
}
if (ast->type == AST_INTERFACE)
- current_module->set_bool_attribute("\\is_interface");
+ current_module->set_bool_attribute(ID::is_interface);
current_module->ast = ast_before_simplify;
current_module->nolatches = flag_nolatches;
current_module->nomeminit = flag_nomeminit;
// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
// new module.
- if (this->get_bool_attribute("\\initial_top")) {
- this->attributes.erase("\\initial_top");
+ if (this->get_bool_attribute(ID::initial_top)) {
+ this->attributes.erase(ID::initial_top);
is_top = true;
}
design->add(newmod);
RTLIL::Module* mod = design->module(original_name);
if (is_top)
- mod->set_bool_attribute("\\top");
+ mod->set_bool_attribute(ID::top);
// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
mod->set_bool_attribute("\\interfaces_replaced_in_module");
// We copy the cell of the interface to the sub-module such that it
// can further be found if it is propagated down to sub-sub-modules etc.
RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name);
- new_subcell->set_bool_attribute("\\is_interface");
+ new_subcell->set_bool_attribute(ID::is_interface);
}
else {
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
if (gen_attributes)
for (auto &attr : that->attributes) {
cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
- cell->setPort("\\A", arg);
+ cell->setPort(ID::A, arg);
cell->parameters["\\Y_WIDTH"] = result_width;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
return wire;
}
sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
if (that != NULL)
for (auto &attr : that->attributes) {
cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
- cell->setPort("\\A", sig);
+ cell->setPort(ID::A, sig);
cell->parameters["\\Y_WIDTH"] = width;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
sig = wire;
}
sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
- cell->setPort("\\A", left);
- cell->setPort("\\B", right);
+ cell->setPort(ID::A, left);
+ cell->setPort(ID::B, right);
cell->parameters["\\Y_WIDTH"] = result_width;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
return wire;
}
sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
- cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
- wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
+ wire->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
- cell->setPort("\\A", right);
- cell->setPort("\\B", left);
- cell->setPort("\\S", cond);
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::A, right);
+ cell->setPort(ID::B, left);
+ cell->setPort(ID::S, cond);
+ cell->setPort(ID::Y, wire);
return wire;
}
{
// generate process and simple root case
proc = new RTLIL::Process;
- proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
+ proc->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT)
for (auto child : always->children)
{
if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
- child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
+ child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) {
found_global_syncs = true;
}
if (child->type == AST_EDGE) {
for (auto child : always->children)
if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
- child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
+ child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk))
continue;
found_clocked_sync = true;
if (found_global_syncs || found_anyedge_syncs)
} while (current_module->wires_.count(wire_name) > 0);
RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
- wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
chunk.wire = wire;
chunk.offset = 0;
case AST_CASE:
{
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
- sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
+ sw->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
current_case->switches.push_back(sw);
RTLIL::CaseRule *backup_case = current_case;
current_case = new RTLIL::CaseRule;
- current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
+ current_case->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
last_generated_case = current_case;
addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
for (auto node : child->children) {
subst_rvalue_map.restore();
}
- if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
+ if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) {
#if 0
// this is a valid transformation, but as optimization it is premature.
// better: add a default case that assigns 'x' to everything, and let later
// This is used by the hierarchy pass to know when it can replace interface connection with the individual
// signals.
RTLIL::Wire *wire = current_module->addWire(str, 1);
- wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->start_offset = 0;
wire->port_id = port_id;
wire->port_input = true;
wire->port_output = true;
- wire->set_bool_attribute("\\is_interface");
+ wire->set_bool_attribute(ID::is_interface);
if (children.size() > 0) {
for(size_t i=0; i<children.size();i++) {
if(children[i]->type == AST_INTERFACEPORTTYPE) {
RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
current_module->connect(wire, val);
- wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
for (auto &attr : attributes) {
log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
- wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->start_offset = range_right;
wire->port_id = port_id;
wire->port_input = is_input;
wire->attributes[attr.first] = attr.second->asAttrConst();
}
- if (is_wand) wire->set_bool_attribute("\\wand");
- if (is_wor) wire->set_bool_attribute("\\wor");
+ if (is_wand) wire->set_bool_attribute(ID::wand);
+ if (is_wor) wire->set_bool_attribute(ID::wor);
}
break;
log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
RTLIL::Memory *memory = new RTLIL::Memory;
- memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ memory->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
memory->name = str;
memory->width = children[0]->range_left - children[0]->range_right + 1;
if (children[1]->range_right < children[1]->range_left) {
if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
RTLIL::Wire *wire = current_module->addWire(str);
- wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->name = str;
if (flag_autowire)
log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
}
else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
RTLIL::Wire *current_wire = current_module->wire(str);
- if (current_wire->get_bool_attribute("\\is_interface"))
+ if (current_wire->get_bool_attribute(ID::is_interface))
is_interface = true;
// Ignore
}
dummy_wire = current_module->wires_[dummy_wire_name];
else {
dummy_wire = current_module->addWire(dummy_wire_name);
- dummy_wire->set_bool_attribute("\\is_interface");
+ dummy_wire->set_bool_attribute(ID::is_interface);
}
RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
return tmp;
sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
- cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
+ cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
- wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
+ wire->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
int mem_width, mem_size, addr_bits;
is_signed = id2ast->is_signed;
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
- cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
int mem_width, mem_size, addr_bits;
id2ast->meminfo(mem_width, mem_size, addr_bits);
}
RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
- cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->setPort("\\A", check);
+ cell->setPort(ID::A, check);
cell->setPort("\\EN", en);
}
break;
log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
RTLIL::Cell *cell = current_module->addCell(str, "");
- cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
cell->set_bool_attribute("\\module_not_derived");
log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
Cell *cell = current_module->addCell(myid, str.substr(1));
- cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
cell->parameters["\\WIDTH"] = width;
if (attributes.count("\\reg")) {
}
Wire *wire = current_module->addWire(myid + "_wire", width);
- wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
- cell->setPort("\\Y", wire);
+ wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
+ cell->setPort(ID::Y, wire);
is_signed = sign_hint;
return SigSpec(wire);
}
// also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
- if (type == AST_MEMORY && (get_bool_attribute("\\mem2reg") || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
+ if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
- if (type == AST_MODULE && get_bool_attribute("\\mem2reg"))
+ if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
children_flags |= AstNode::MEM2REG_FL_ALL;
dict<AstNode*, uint32_t> *proc_flags_p = NULL;
for (auto cell : module->cells())
if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
- module->connect(cell->getPort("\\Y"), cell->getPort("\\A"));
+ module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
remove_cells.push_back(cell);
}
sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
sopcell->parameters["\\DEPTH"] = 0;
sopcell->parameters["\\TABLE"] = RTLIL::Const();
- sopcell->setPort("\\A", input_sig);
- sopcell->setPort("\\Y", output_sig);
+ sopcell->setPort(ID::A, input_sig);
+ sopcell->setPort(ID::Y, output_sig);
sopmode = -1;
lastcell = sopcell;
}
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
- cell->setPort("\\A", input_sig);
- cell->setPort("\\Y", output_sig);
+ cell->setPort(ID::A, input_sig);
+ cell->setPort(ID::Y, output_sig);
lutptr = &cell->parameters.at("\\LUT");
lut_default_state = RTLIL::State::Sx;
lastcell = cell;
if (sopmode == -1) {
sopmode = (*output == '1');
if (!sopmode) {
- SigSpec outnet = sopcell->getPort("\\Y");
+ SigSpec outnet = sopcell->getPort(ID::Y);
SigSpec tempnet = module->addWire(NEW_ID);
module->addNotGate(NEW_ID, tempnet, outnet);
- sopcell->setPort("\\Y", tempnet);
+ sopcell->setPort(ID::Y, tempnet);
}
} else
log_assert(sopmode == (*output == '1'));
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
- cell->setPort("\\A", A);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
- cell->setPort("\\A", A);
- cell->setPort("\\B", B);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::B, B);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
- cell->setPort("\\A", A);
- cell->setPort("\\B", B);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::B, B);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
- cell->setPort("\\A", A);
- cell->setPort("\\B", B);
- cell->setPort("\\Y", module->addWire(NEW_ID));
- return cell->getPort("\\Y");
+ cell->setPort(ID::A, A);
+ cell->setPort(ID::B, B);
+ cell->setPort(ID::Y, module->addWire(NEW_ID));
+ return cell->getPort(ID::Y);
}
static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
- clk_sig = it.second->getPort("\\A");
+ if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clk_sig) {
+ clk_sig = it.second->getPort(ID::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
- clear_sig = it.second->getPort("\\A");
+ if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
+ clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
- preset_sig = it.second->getPort("\\A");
+ if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
+ preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
- cell->setPort("\\A", iq_sig);
- cell->setPort("\\Y", iqn_sig);
+ cell->setPort(ID::A, iq_sig);
+ cell->setPort(ID::Y, iqn_sig);
cell = module->addCell(NEW_ID, "");
cell->setPort("\\D", data_sig);
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
- cell->setPort("\\S", preset_sig);
+ cell->setPort(ID::S, preset_sig);
cell->setPort("\\R", clear_sig);
}
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
- enable_sig = it.second->getPort("\\A");
+ if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == enable_sig) {
+ enable_sig = it.second->getPort(ID::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
- clear_sig = it.second->getPort("\\A");
+ if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
+ clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
- preset_sig = it.second->getPort("\\A");
+ if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
+ preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
- cell->setPort("\\A", iq_sig);
- cell->setPort("\\Y", iqn_sig);
+ cell->setPort(ID::A, iq_sig);
+ cell->setPort(ID::Y, iqn_sig);
if (clear_sig.size() == 1)
{
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
- inv->setPort("\\A", clear_sig);
- inv->setPort("\\Y", module->addWire(NEW_ID));
+ inv->setPort(ID::A, clear_sig);
+ inv->setPort(ID::Y, module->addWire(NEW_ID));
if (clear_polarity == true)
- clear_negative = inv->getPort("\\Y");
+ clear_negative = inv->getPort(ID::Y);
if (clear_polarity != enable_polarity)
- clear_enable = inv->getPort("\\Y");
+ clear_enable = inv->getPort(ID::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
- data_gate->setPort("\\A", data_sig);
- data_gate->setPort("\\B", clear_negative);
- data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ data_gate->setPort(ID::A, data_sig);
+ data_gate->setPort(ID::B, clear_negative);
+ data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
- enable_gate->setPort("\\A", enable_sig);
- enable_gate->setPort("\\B", clear_enable);
- enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ enable_gate->setPort(ID::A, enable_sig);
+ enable_gate->setPort(ID::B, clear_enable);
+ enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
if (preset_sig.size() == 1)
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
- inv->setPort("\\A", preset_sig);
- inv->setPort("\\Y", module->addWire(NEW_ID));
+ inv->setPort(ID::A, preset_sig);
+ inv->setPort(ID::Y, module->addWire(NEW_ID));
if (preset_polarity == false)
- preset_positive = inv->getPort("\\Y");
+ preset_positive = inv->getPort(ID::Y);
if (preset_polarity != enable_polarity)
- preset_enable = inv->getPort("\\Y");
+ preset_enable = inv->getPort(ID::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
- data_gate->setPort("\\A", data_sig);
- data_gate->setPort("\\B", preset_positive);
- data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ data_gate->setPort(ID::A, data_sig);
+ data_gate->setPort(ID::B, preset_positive);
+ data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
- enable_gate->setPort("\\A", enable_sig);
- enable_gate->setPort("\\B", preset_enable);
- enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
+ enable_gate->setPort(ID::A, enable_sig);
+ enable_gate->setPort(ID::B, preset_enable);
+ enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
module.second->name = mangled_name;
module.second->design = design;
- module.second->attributes.erase("\\top");
+ module.second->attributes.erase(ID::top);
design->modules_[mangled_name] = module.second;
derived_design->modules_.erase(module.first);
}
Att *attr;
if (obj->Linefile())
- attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
+ attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
// FIXME: Parse numeric attributes
FOREACH_ATTRIBUTE(obj, mi, attr) {
wire->str = ast_stack.back()->children.back()->str;
if (ast_stack.back()->children.back()->is_input) {
AstNode *n = ast_stack.back()->children.back();
- if (n->attributes.count("\\defaultvalue"))
- delete n->attributes.at("\\defaultvalue");
- n->attributes["\\defaultvalue"] = $2;
+ if (n->attributes.count(ID::defaultvalue))
+ delete n->attributes.at(ID::defaultvalue);
+ n->attributes[ID::defaultvalue] = $2;
} else
if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
bool attr_anyseq = false;
bool attr_allconst = false;
bool attr_allseq = false;
- if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) {
- delete ast_stack.back()->children.back()->attributes.at("\\anyconst");
- ast_stack.back()->children.back()->attributes.erase("\\anyconst");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyconst)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::anyconst);
+ ast_stack.back()->children.back()->attributes.erase(ID::anyconst);
attr_anyconst = true;
}
- if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) {
- delete ast_stack.back()->children.back()->attributes.at("\\anyseq");
- ast_stack.back()->children.back()->attributes.erase("\\anyseq");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::anyseq)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::anyseq);
+ ast_stack.back()->children.back()->attributes.erase(ID::anyseq);
attr_anyseq = true;
}
- if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) {
- delete ast_stack.back()->children.back()->attributes.at("\\allconst");
- ast_stack.back()->children.back()->attributes.erase("\\allconst");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::allconst)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::allconst);
+ ast_stack.back()->children.back()->attributes.erase(ID::allconst);
attr_allconst = true;
}
- if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) {
- delete ast_stack.back()->children.back()->attributes.at("\\allseq");
- ast_stack.back()->children.back()->attributes.erase("\\allseq");
+ if (ast_stack.back()->children.back()->get_bool_attribute(ID::allseq)) {
+ delete ast_stack.back()->children.back()->attributes.at(ID::allseq);
+ ast_stack.back()->children.back()->attributes.erase(ID::allseq);
attr_allseq = true;
}
if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) {
AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str;
if (astbuf1->is_input) {
- if (astbuf1->attributes.count("\\defaultvalue"))
- delete astbuf1->attributes.at("\\defaultvalue");
- astbuf1->attributes["\\defaultvalue"] = $3;
+ if (astbuf1->attributes.count(ID::defaultvalue))
+ delete astbuf1->attributes.at(ID::defaultvalue);
+ astbuf1->attributes[ID::defaultvalue] = $3;
}
else if (astbuf1->is_reg || astbuf1->is_logic){
AstNode *assign = new AstNode(AST_ASSIGN_LE, wire, $3);
opt_synopsys_attr:
opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
- if (ast_stack.back()->attributes.count("\\full_case") == 0)
- ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
+ if (ast_stack.back()->attributes.count(ID::full_case) == 0)
+ ast_stack.back()->attributes[ID::full_case] = AstNode::mkconst_int(1, false);
} |
opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
- if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
- ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
+ if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
+ ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
} |
/* empty */;
for (auto cell : constr_cells)
while (true)
{
- SigSpec A = sigmap(cell->getPort("\\A"));
+ SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort("\\EN"));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
if (A_map.second != EN_map.second)
break;
- cell->setPort("\\A", A_map.first);
+ cell->setPort(ID::A, A_map.first);
cell->setPort("\\EN", EN_map.first);
}
}
for (auto cell : constr_cells)
for (int i = 0; i < mode_arg; i++)
{
- SigSpec orig_a = cell->getPort("\\A");
+ SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort("\\EN");
Wire *new_a = module->addWire(NEW_ID);
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
- cell->setPort("\\A", new_a);
+ cell->setPort(ID::A, new_a);
cell->setPort("\\EN", new_en);
}
}
if (import_mode) {
for (auto module : copy_src_modules)
{
- if (module->get_bool_attribute("\\top")) {
+ if (module->get_bool_attribute(ID::top)) {
copy_src_modules.clear();
copy_src_modules.push_back(module);
break;
RTLIL::Module *t = mod->clone();
t->name = prefix;
t->design = copy_to_design;
- t->attributes.erase("\\top");
+ t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
RTLIL::Module *t = fmod->clone();
t->name = trg_name;
t->design = copy_to_design;
- t->attributes.erase("\\top");
+ t->attributes.erase(ID::top);
copy_to_design->add(t);
queue.insert(t);
}
std::string proc_src = RTLIL::unescape_id(proc->name);
- if (proc->attributes.count("\\src") > 0)
- proc_src = proc->attributes.at("\\src").decode_string();
+ if (proc->attributes.count(ID::src) > 0)
+ proc_src = proc->attributes.at(ID::src).decode_string();
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str());
}
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
- cell->setPort("\\A", sig_a);
- cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
- new_sig = cell->getPort("\\Y");
+ cell->setPort(ID::A, sig_a);
+ cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
+ new_sig = cell->getPort(ID::Y);
}
sliced_signals_cache[sig] = new_sig;
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
- cell->setPort("\\A", new_sig);
- cell->setPort("\\B", sig2);
- cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
- new_sig = cell->getPort("\\Y");
+ cell->setPort(ID::A, new_sig);
+ cell->setPort(ID::B, sig2);
+ cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
+ new_sig = cell->getPort(ID::Y);
}
spliced_signals_cache[sig] = new_sig;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
- if (wire->attributes.count("\\src"))
- new_wire->attributes["\\src"] = wire->attributes.at("\\src");
+ if (wire->attributes.count(ID::src))
+ new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
if (wire->attributes.count("\\keep"))
new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
"$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) {
- int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
- int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
- int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
+ int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0;
+ int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0;
+ int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
- cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));
+ cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y)));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
}
for (auto mod : design->selected_modules())
{
if (!top_mod && design->full_selection())
- if (mod->get_bool_attribute("\\top"))
+ if (mod->get_bool_attribute(ID::top))
top_mod = mod;
statdata_t data(design, mod, width_mode, cell_area, techname);
cell_warn_cache.insert(cell);
}
if (cell->type == "$equiv") {
- SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
if (bit_a != bit_b) {
int ez_a = satgen.importSigBit(bit_a, step);
int ez_b = satgen.importSigBit(bit_b, step);
if (!ez->solve(new_step_not_consistent)) {
log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset));
for (auto cell : workset)
- cell->setPort("\\B", cell->getPort("\\A"));
+ cell->setPort(ID::B, cell->getPort(ID::A));
success_counter += GetSize(workset);
return;
}
for (auto cell : workset)
{
- SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
- log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y"))));
+ log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y))));
int ez_a = satgen.importSigBit(bit_a, max_seq+1);
int ez_b = satgen.importSigBit(bit_b, max_seq+1);
if (!ez->solve(cond)) {
log(" success!\n");
- cell->setPort("\\B", cell->getPort("\\A"));
+ cell->setPort(ID::B, cell->getPort(ID::A));
success_counter++;
} else {
log(" failed.\n");
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- if (cell->getPort("\\A") != cell->getPort("\\B"))
+ if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.insert(cell);
}
{
auto cell = module->cell(cell_name);
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
if (sig_a == sig_b) {
for (auto bit : sig_a)
if (cell_regions.count(cell->name) || cell->type != "$equiv")
continue;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
log_assert(sig_a != sig_b);
for (auto &conn : c->connections()) {
if (!ct.cell_input(c->type, conn.first))
continue;
- if (c->type == "$equiv" && (conn.first == "\\A") != gold_mode)
+ if (c->type == "$equiv" && (conn.first == ID::A) != gold_mode)
continue;
for (auto bit : sigmap(conn.second))
if (bit_to_driver.count(bit))
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
- if (c->type == "$equiv" && c->getPort("\\A") != c->getPort("\\B"))
+ if (c->type == "$equiv" && c->getPort(ID::A) != c->getPort(ID::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
- miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx),
- miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B"))) :
- miter_module->Eq(NEW_ID, c->getPort("\\A"), c->getPort("\\B"));
+ miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
+ miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
+ miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) {
- string cmp_name = string("\\cmp") + log_signal(c->getPort("\\Y"));
+ string cmp_name = string("\\cmp") + log_signal(c->getPort(ID::Y));
for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\')
cmp_name[i] = '_';
continue;
}
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
if (sig_a == sig_b)
continue;
for (auto bit : sig_y)
visited.insert(bit);
- cell->setPort("\\Y", make_output(sig_y, cell->name));
+ cell->setPort(ID::Y, make_output(sig_y, cell->name));
}
SigSpec srcsig;
for (auto cell : module->cells())
if (cell->type == "$equiv")
- cell->setPort("\\Y", rewrite_sigmap(sigmap(cell->getPort("\\Y"))));
+ cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
module->fixup_ports();
}
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort("\\A") == cell->getPort("\\B"))) {
- log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort("\\Y")));
- module->connect(cell->getPort("\\Y"), mode_gate ? cell->getPort("\\B") : cell->getPort("\\A"));
+ if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
+ log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
+ module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell);
remove_count++;
}
bool run_cell()
{
- SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
- SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
+ SigBit bit_a = sigmap(equiv_cell->getPort(ID::A)).as_bit();
+ SigBit bit_b = sigmap(equiv_cell->getPort(ID::B)).as_bit();
int ez_context = ez->frozen_literal();
if (satgen.model_undef)
if (verbose) {
log(" Trying to prove $equiv cell %s:\n", log_id(equiv_cell));
- log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort("\\Y")));
+ log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(equiv_cell->getPort(ID::Y)));
} else {
- log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort("\\Y")));
+ log(" Trying to prove $equiv for %s:", log_signal(equiv_cell->getPort(ID::Y)));
}
int step = max_seq;
if (!ez->solve(ez_context)) {
log(verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
- equiv_cell->setPort("\\B", equiv_cell->getPort("\\A"));
+ equiv_cell->setPort(ID::B, equiv_cell->getPort(ID::A));
ez->assume(ez->NOT(ez_context));
return true;
}
if (GetSize(equiv_cells) > 1) {
SigSpec sig;
for (auto c : equiv_cells)
- sig.append(sigmap(c->getPort("\\Y")));
+ sig.append(sigmap(c->getPort(ID::Y)));
log(" Grouping SAT models for %s:\n", log_signal(sig));
}
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
- auto bit = sigmap(cell->getPort("\\Y").as_bit());
+ if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) {
+ auto bit = sigmap(cell->getPort(ID::Y).as_bit());
auto bit_group = bit;
if (!nogroup && bit_group.wire)
bit_group.offset = 0;
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- if (cell->getPort("\\A") != cell->getPort("\\B"))
+ if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.push_back(cell);
else
proven_equiv_cells++;
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
- log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort("\\A")), log_signal(cell->getPort("\\B")));
+ log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
}
unproven_count += GetSize(unproven_equiv_cells);
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
- SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
+ SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
- SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
- SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
+ SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
+ SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
+ SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
module->connect(sig_y, sig_a);
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list)
{
- if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") {
+ if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) {
goto ret_false;
}
recursion_monitor.insert(cellport.first);
- RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
+ RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
+ RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
- if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig)
+ if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig)
continue;
- if (cellport.second != "\\A" && cellport.second != "\\B")
+ if (cellport.second != ID::A && cellport.second != ID::B)
return false;
- if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
+ if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y))
return false;
for (auto &port_it : cell->connections())
- if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
+ if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
return false;
- if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
+ if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
continue;
- if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
+ if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
continue;
return false;
}
static void detect_fsm(RTLIL::Wire *wire)
{
- bool has_fsm_encoding_attr = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() != "none";
- bool has_fsm_encoding_none = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() == "none";
+ bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
+ bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
bool has_init_attr = wire->attributes.count("\\init") > 0;
bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
bool looks_like_state_reg = false, looks_like_good_state_reg = false;
if (wire->width <= 1) {
if (has_fsm_encoding_attr) {
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
- wire->attributes.erase("\\fsm_encoding");
+ wire->attributes.erase(ID::fsm_encoding);
}
return;
}
if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
{
log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
- wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
+ wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
}
else
if (looks_like_state_reg)
return true;
if (cell->type.in("$mux", "$pmux"))
- if (cell->getPort("\\A").size() < 2)
+ if (cell->getPort(ID::A).size() < 2)
return true;
int in_bits = 0;
RTLIL::SigSpec new_signals;
- if (cell->hasPort("\\A")) {
- in_bits += GetSize(cell->getPort("\\A"));
- new_signals.append(assign_map(cell->getPort("\\A")));
+ if (cell->hasPort(ID::A)) {
+ in_bits += GetSize(cell->getPort(ID::A));
+ new_signals.append(assign_map(cell->getPort(ID::A)));
}
- if (cell->hasPort("\\B")) {
- in_bits += GetSize(cell->getPort("\\B"));
- new_signals.append(assign_map(cell->getPort("\\B")));
+ if (cell->hasPort(ID::B)) {
+ in_bits += GetSize(cell->getPort(ID::B));
+ new_signals.append(assign_map(cell->getPort(ID::B)));
}
- if (cell->hasPort("\\S")) {
- in_bits += GetSize(cell->getPort("\\S"));
- new_signals.append(assign_map(cell->getPort("\\S")));
+ if (cell->hasPort(ID::S)) {
+ in_bits += GetSize(cell->getPort(ID::S));
+ new_signals.append(assign_map(cell->getPort(ID::S)));
}
if (in_bits > 8)
return false;
- if (cell->hasPort("\\Y"))
- new_signals.append(assign_map(cell->getPort("\\Y")));
+ if (cell->hasPort(ID::Y))
+ new_signals.append(assign_map(cell->getPort(ID::Y)));
new_signals.sort_and_unify();
new_signals.remove_const();
if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0)
continue;
for (auto &p : c->connections()) {
- if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y")
+ if (p.first != ID::A && p.first != ID::B && p.first != ID::S && p.first != ID::Y)
goto next_cell;
}
if (!is_cell_merge_candidate(c)) {
for (int i = 0; i < (1 << input_sig.size()); i++) {
RTLIL::Const in_val(i, input_sig.size());
RTLIL::SigSpec A, B, S;
- if (cell->hasPort("\\A"))
- A = assign_map(cell->getPort("\\A"));
- if (cell->hasPort("\\B"))
- B = assign_map(cell->getPort("\\B"));
- if (cell->hasPort("\\S"))
- S = assign_map(cell->getPort("\\S"));
+ if (cell->hasPort(ID::A))
+ A = assign_map(cell->getPort(ID::A));
+ if (cell->hasPort(ID::B))
+ B = assign_map(cell->getPort(ID::B));
+ if (cell->hasPort(ID::S))
+ S = assign_map(cell->getPort(ID::S));
A.replace(input_sig, RTLIL::SigSpec(in_val));
B.replace(input_sig, RTLIL::SigSpec(in_val));
S.replace(input_sig, RTLIL::SigSpec(in_val));
for (auto &cellport : cellport_list)
{
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") {
+ if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
}
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
- RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
+ RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_aa = sig;
sig_aa.replace(sig_y, sig_a);
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b;
- if (cell->hasPort("\\B"))
- sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
- if (cellport.second == "\\A" && !sig_b.is_fully_const())
+ if (cell->hasPort(ID::B))
+ sig_b = assign_map(cell->getPort(ID::B));
+ RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
+ if (cellport.second == ID::A && !sig_b.is_fully_const())
continue;
- if (cellport.second == "\\B" && !sig_a.is_fully_const())
+ if (cellport.second == ID::B && !sig_a.is_fully_const())
continue;
log(" found ctrl output: %s\n", log_signal(sig_y));
ctrl_out.append(sig_y);
// rename original state wire
module->wires_.erase(wire->name);
- wire->attributes.erase("\\fsm_encoding");
+ wire->attributes.erase(ID::fsm_encoding);
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
module->wires_[wire->name] = wire;
assign_map.apply(sig);
sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
- if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort("\\Y") &&
- cell->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+ if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) &&
+ cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
}
if (cell->type == "$pmux") {
- RTLIL::SigSpec sel_sig = assign_map(cell->getPort("\\S"));
+ RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)
if (bit1 != bit2)
std::vector<RTLIL::Wire*> wire_list;
for (auto &wire_it : module->wires_)
- if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none")
+ if (wire_it.second->attributes.count(ID::fsm_encoding) > 0 && wire_it.second->attributes[ID::fsm_encoding].decode_string() != "none")
if (design->selected(module, wire_it.second))
wire_list.push_back(wire_it.second);
for (auto wire : wire_list)
and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
- eq_cell->setPort("\\A", eq_sig_a);
- eq_cell->setPort("\\B", eq_sig_b);
- eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
+ eq_cell->setPort(ID::A, eq_sig_a);
+ eq_cell->setPort(ID::B, eq_sig_b);
+ eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
- or_cell->setPort("\\A", or_sig);
- or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
+ or_cell->setPort(ID::A, or_sig);
+ or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
- and_cell->setPort("\\A", and_sig.extract(0, 1));
- and_cell->setPort("\\B", and_sig.extract(1, 1));
- and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
+ and_cell->setPort(ID::A, and_sig.extract(0, 1));
+ and_cell->setPort(ID::B, and_sig.extract(1, 1));
+ and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
- or_cell->setPort("\\A", cases_vector);
- or_cell->setPort("\\Y", output);
+ or_cell->setPort(ID::A, cases_vector);
+ or_cell->setPort(ID::Y, output);
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
- eq_cell->setPort("\\A", sig_a);
- eq_cell->setPort("\\B", sig_b);
- eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
+ eq_cell->setPort(ID::A, sig_a);
+ eq_cell->setPort(ID::B, sig_b);
+ eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
}
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");
- mux_cell->setPort("\\A", sig_a);
- mux_cell->setPort("\\B", sig_b);
- mux_cell->setPort("\\S", sig_s);
- mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
+ mux_cell->setPort(ID::A, sig_a);
+ mux_cell->setPort(ID::B, sig_b);
+ mux_cell->setPort(ID::S, sig_s);
+ mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
}
static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding)
{
- std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";
+ std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto";
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
// reprocess the module:
if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) {
for (auto wire : module->wires()) {
- if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface"))
+ if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface))
has_interface_ports = true;
}
}
dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
for (auto cell : module->cells())
{
- if(cell->get_bool_attribute("\\is_interface")) {
+ if(cell->get_bool_attribute(ID::is_interface)) {
RTLIL::Module *intf_module = design->module(cell->type);
interfaces_in_module[cell->name] = intf_module;
}
// Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to
// some lists, so that the ports for sub-modules can be replaced further down:
for (auto &conn : cell->connections()) {
- if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
+ if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list
//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
//}
for (auto &d : interface_modport_pool) {
interface_modport = "\\" + d;
}
- if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module
+ if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute(ID::is_interface)) { // Check if the connected wire is a potential interface in the parent module
std::string interface_name_str = conn.second.bits()[0].wire->name.str();
interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
interface_name_str = "\\" + interface_name_str;
if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) {
// If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:",
// so that the signals of the interface are added to the parent module.
- if (mod->get_bool_attribute("\\is_interface")) {
+ if (mod->get_bool_attribute(ID::is_interface)) {
goto handle_interface_instance;
}
continue;
// We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter
// an interface instance:
- if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) {
- cell->set_bool_attribute("\\is_interface");
+ if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute("\\module_not_derived")) {
+ cell->set_bool_attribute(ID::is_interface);
RTLIL::Module *derived_module = design->module(cell->type);
interfaces_in_module[cell->name] = derived_module;
did_something = true;
// safe to delete all of the remaining dummy interface ports:
pool<RTLIL::Wire*> del_wires;
for(auto wire : mod->wires()) {
- if ((wire->port_input || wire->port_output) && wire->get_bool_attribute("\\is_interface")) {
+ if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) {
del_wires.insert(wire);
}
}
RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod)
{
- if(top_mod != NULL && top_mod->get_bool_attribute("\\initial_top"))
+ if(top_mod != NULL && top_mod->get_bool_attribute(ID::initial_top))
return top_mod;
else {
for (auto mod : design->modules()) {
- if (mod->get_bool_attribute("\\top")) {
+ if (mod->get_bool_attribute(ID::top)) {
return mod;
}
}
if (top_mod == nullptr)
for (auto mod : design->modules())
- if (mod->get_bool_attribute("\\top"))
+ if (mod->get_bool_attribute(ID::top))
top_mod = mod;
if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
if (top_mod != NULL) {
for (auto mod : design->modules())
if (mod == top_mod)
- mod->attributes["\\initial_top"] = RTLIL::Const(1);
+ mod->attributes[ID::initial_top] = RTLIL::Const(1);
else
- mod->attributes.erase("\\initial_top");
+ mod->attributes.erase(ID::initial_top);
}
bool did_something = true;
if (top_mod != NULL) {
for (auto mod : design->modules()) {
if (mod == top_mod)
- mod->attributes["\\top"] = RTLIL::Const(1);
+ mod->attributes[ID::top] = RTLIL::Const(1);
else
- mod->attributes.erase("\\top");
- mod->attributes.erase("\\initial_top");
+ mod->attributes.erase(ID::top);
+ mod->attributes.erase(ID::initial_top);
}
}
{
for (auto module : design->modules())
for (auto wire : module->wires())
- if (wire->port_input && wire->attributes.count("\\defaultvalue"))
- defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
+ if (wire->port_input && wire->attributes.count(ID::defaultvalue))
+ defaults_db[module->name][wire->name] = wire->attributes.at(ID::defaultvalue);
}
// Process SV implicit wildcard port connections
std::set<Module*> blackbox_derivatives;
for (auto wire : module->wires())
{
- if (wire->get_bool_attribute("\\wand")) {
+ if (wire->get_bool_attribute(ID::wand)) {
wand_map[wire] = SigSpec();
wand_wor_index.insert(wire);
}
- if (wire->get_bool_attribute("\\wor")) {
+ if (wire->get_bool_attribute(ID::wor)) {
wor_map[wire] = SigSpec();
wand_wor_index.insert(wire);
}
for (auto module : design->selected_modules())
{
- if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute("\\top"))
+ if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute(ID::top))
continue;
for (auto cell : module->selected_cells())
do {
bool enable_invert = mux_cells_a.count(sig_data) != 0;
Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
- check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
- sig_data = sigmap(mux->getPort("\\Y"));
- en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
+ check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A)));
+ sig_data = sigmap(mux->getPort(ID::Y));
+ en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S));
} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
for (auto bit : sig_data)
if (cell->type == "$dff")
dff_cells.push_back(cell);
if (cell->type == "$mux") {
- mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
- mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
+ mux_cells_a[sigmap(cell->getPort(ID::A))] = cell;
+ mux_cells_b[sigmap(cell->getPort(ID::B))] = cell;
}
- if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_y = cell->getPort("\\Y");
+ if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort(ID::A)) == 1)) {
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_y = cell->getPort(ID::Y);
if (cell->type == "$not")
sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
if (cell->type == "$logic_not")
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- c->setPort("\\Y", rd_signals[k]);
- c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1));
+ c->setPort(ID::Y, rd_signals[k]);
+ c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1));
count_mux++;
- c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
- c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
+ c->setPort(ID::A, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
+ c->setPort(ID::B, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
- next_rd_signals.push_back(c->getPort("\\A"));
- next_rd_signals.push_back(c->getPort("\\B"));
+ next_rd_signals.push_back(c->getPort(ID::A));
+ next_rd_signals.push_back(c->getPort(ID::B));
}
next_rd_signals.swap(rd_signals);
c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- c->setPort("\\A", w);
- c->setPort("\\B", wr_bit);
+ c->setPort(ID::A, w);
+ c->setPort(ID::B, wr_bit);
w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
- c->setPort("\\Y", RTLIL::SigSpec(w));
+ c->setPort(ID::Y, RTLIL::SigSpec(w));
}
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
c->parameters["\\WIDTH"] = wr_width;
- c->setPort("\\A", sig.extract(wr_offset, wr_width));
- c->setPort("\\B", wr_data.extract(wr_offset, wr_width));
- c->setPort("\\S", RTLIL::SigSpec(w));
+ c->setPort(ID::A, sig.extract(wr_offset, wr_width));
+ c->setPort(ID::B, wr_data.extract(wr_offset, wr_width));
+ c->setPort(ID::S, RTLIL::SigSpec(w));
w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
- c->setPort("\\Y", w);
+ c->setPort(ID::Y, w);
sig.replace(wr_offset, w);
wr_offset += wr_width;
RTLIL::Cell *cell = sig_to_mux.at(sig).first;
int bit_idx = sig_to_mux.at(sig).second;
- std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
- std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
- std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
log_assert(sig_y.at(bit_idx) == sig);
for (int i = 0; i < int(sig_s.size()); i++)
if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
- RTLIL::SigSpec new_b = cell->getPort("\\B");
+ RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
- cell->setPort("\\B", new_b);
+ cell->setPort(ID::B, new_b);
}
return false;
}
new_state[sig_s[i]] = true;
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
- RTLIL::SigSpec new_b = cell->getPort("\\B");
+ RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
- cell->setPort("\\B", new_b);
+ cell->setPort(ID::B, new_b);
}
}
new_state[sig_s[i]] = false;
if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
- RTLIL::SigSpec new_a = cell->getPort("\\A");
+ RTLIL::SigSpec new_a = cell->getPort(ID::A);
new_a.replace(bit_idx, RTLIL::State::Sx);
- cell->setPort("\\A", new_a);
+ cell->setPort(ID::A, new_a);
}
return false;
if (cell->type.in("$mux", "$pmux"))
{
- std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
- std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
- std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
non_feedback_nets.insert(sig_s.begin(), sig_s.end());
if (cell->type == "$mux")
{
- RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
+ RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
if (sig_a.is_fully_undef())
- sigmap_xmux.add(cell->getPort("\\Y"), sig_b);
+ sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
else if (sig_b.is_fully_undef())
- sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
+ sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
}
if (cell->type.in("$mux", "$pmux"))
{
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < int(sig_y.size()); i++)
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
}
Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER");
pm.module->swap_names(cell, st.carry);
- cell->setPort("\\A", st.carry->getPort("\\I0"));
- cell->setPort("\\B", st.carry->getPort("\\I1"));
+ cell->setPort(ID::A, st.carry->getPort("\\I0"));
+ cell->setPort(ID::B, st.carry->getPort("\\I1"));
auto CI = st.carry->getPort("\\CI");
cell->setPort("\\CI", CI);
cell->setPort("\\CO", st.carry->getPort("\\CO"));
for (auto cell : mod->cells())
{
- if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ if (cell->type == "$reduce_or" && cell->getPort(ID::Y) == signal)
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
- if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ if (cell->type == "$reduce_bool" && cell->getPort(ID::Y) == signal)
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
- if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
+ if (cell->type == "$logic_not" && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
- if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
+ if (cell->type == "$not" && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
- if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) {
- if (cell->getPort("\\A").is_fully_const()) {
- if (!cell->getPort("\\A").as_bool())
+ if (cell->type.in("$eq", "$eqx") && cell->getPort(ID::Y) == signal) {
+ if (cell->getPort(ID::A).is_fully_const()) {
+ if (!cell->getPort(ID::A).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\B"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::B), ref, polarity);
}
- if (cell->getPort("\\B").is_fully_const()) {
- if (!cell->getPort("\\B").as_bool())
+ if (cell->getPort(ID::B).is_fully_const()) {
+ if (!cell->getPort(ID::B).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
}
- if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) {
- if (cell->getPort("\\A").is_fully_const()) {
- if (cell->getPort("\\A").as_bool())
+ if (cell->type.in("$ne", "$nex") && cell->getPort(ID::Y) == signal) {
+ if (cell->getPort(ID::A).is_fully_const()) {
+ if (cell->getPort(ID::A).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\B"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::B), ref, polarity);
}
- if (cell->getPort("\\B").is_fully_const()) {
- if (cell->getPort("\\B").as_bool())
+ if (cell->getPort(ID::B).is_fully_const()) {
+ if (cell->getPort(ID::B).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
}
}
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", sync_low_signals);
- cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID));
+ cell->setPort(ID::A, sync_low_signals);
+ cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
}
if (sync_low_signals.size() > 0) {
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", sync_low_signals);
- cell->setPort("\\Y", mod->addWire(NEW_ID));
- sync_high_signals.append(cell->getPort("\\Y"));
+ cell->setPort(ID::A, sync_low_signals);
+ cell->setPort(ID::Y, mod->addWire(NEW_ID));
+ sync_high_signals.append(cell->getPort(ID::Y));
}
if (sync_high_signals.size() > 1) {
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", sync_high_signals);
- cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID));
+ cell->setPort(ID::A, sync_high_signals);
+ cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
}
RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
- inv_cell->setPort("\\A", sync_value);
- inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
+ inv_cell->setPort(ID::A, sync_value);
+ inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
- mux_set_cell->setPort("\\A", sig_sr_set);
- mux_set_cell->setPort("\\B", sync_value);
- mux_set_cell->setPort("\\S", sync_high_signals);
- mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
+ mux_set_cell->setPort(ID::A, sig_sr_set);
+ mux_set_cell->setPort(ID::B, sync_value);
+ mux_set_cell->setPort(ID::S, sync_high_signals);
+ mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
- mux_clr_cell->setPort("\\A", sig_sr_clr);
- mux_clr_cell->setPort("\\B", sync_value_inv);
- mux_clr_cell->setPort("\\S", sync_high_signals);
- mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
+ mux_clr_cell->setPort(ID::A, sig_sr_clr);
+ mux_clr_cell->setPort(ID::B, sync_value_inv);
+ mux_clr_cell->setPort(ID::S, sync_high_signals);
+ mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
}
std::stringstream sstr;
inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
- inv_set->setPort("\\A", sig_set);
- inv_set->setPort("\\Y", sig_set_inv);
+ inv_set->setPort(ID::A, sig_set);
+ inv_set->setPort(ID::Y, sig_set_inv);
RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
- mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
- mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set);
- mux_sr_set->setPort("\\Y", sig_sr_set);
- mux_sr_set->setPort("\\S", set);
+ mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
+ mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
+ mux_sr_set->setPort(ID::Y, sig_sr_set);
+ mux_sr_set->setPort(ID::S, set);
RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
- mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
- mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv);
- mux_sr_clr->setPort("\\Y", sig_sr_clr);
- mux_sr_clr->setPort("\\S", set);
+ mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
+ mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
+ mux_sr_clr->setPort(ID::Y, sig_sr_clr);
+ mux_sr_clr->setPort(ID::S, set);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", inputs);
- cell->setPort("\\B", compare);
- cell->setPort("\\Y", sync_level->signal);
+ cell->setPort(ID::A, inputs);
+ cell->setPort(ID::B, compare);
+ cell->setPort(ID::Y, sync_level->signal);
many_async_rules.clear();
}
{
if (cell->type.in("$mux", "$pmux"))
{
- auto sig_y = sigmap(cell->getPort("\\Y"));
+ auto sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++)
mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
pool<SigBit> mux_srcbits_pool;
- for (auto bit : sigmap(cell->getPort("\\A")))
+ for (auto bit : sigmap(cell->getPort(ID::A)))
mux_srcbits_pool.insert(bit);
- for (auto bit : sigmap(cell->getPort("\\B")))
+ for (auto bit : sigmap(cell->getPort(ID::B)))
mux_srcbits_pool.insert(bit);
vector<SigBit> mux_srcbits_vec;
Cell *cell = it->second.first;
int index = it->second.second;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_s = sigmap(cell->getPort("\\S"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_s = sigmap(cell->getPort(ID::S));
int width = GetSize(sig_a);
pool<int> children;
int n = find_mux_feedback(sig_a[index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_a[index] == needle) {
- SigSpec sig = cell->getPort("\\A");
+ SigSpec sig = cell->getPort(ID::A);
sig[index] = State::Sx;
- cell->setPort("\\A", sig);
+ cell->setPort(ID::A, sig);
}
for (int i = 0; i < GetSize(sig_s); i++)
n = make_inner(sig_s[i], State::S0, n);
n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_b[i*width + index] == needle) {
- SigSpec sig = cell->getPort("\\B");
+ SigSpec sig = cell->getPort(ID::B);
sig[i*width + index] = State::Sx;
- cell->setPort("\\B", sig);
+ cell->setPort(ID::B, sig);
}
children.insert(make_inner(sig_s[i], State::S1, n));
}
void fixup_mux(Cell *cell)
{
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_b = cell->getPort("\\B");
- SigSpec sig_s = cell->getPort("\\S");
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_b = cell->getPort(ID::B);
+ SigSpec sig_s = cell->getPort(ID::S);
SigSpec sig_any_valid_b;
SigSpec sig_new_b, sig_new_s;
}
if (sig_a.is_fully_undef() && !sig_any_valid_b.empty())
- cell->setPort("\\A", sig_any_valid_b);
+ cell->setPort(ID::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) {
cell->type = "$mux";
cell->setParam("\\S_WIDTH", GetSize(sig_new_s));
}
- cell->setPort("\\B", sig_new_b);
- cell->setPort("\\S", sig_new_s);
+ cell->setPort(ID::B, sig_new_b);
+ cell->setPort(ID::S, sig_new_s);
}
void fixup_muxes()
void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
{
cell->attributes = sw->attributes;
- cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src"));
+ cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src));
}
RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- eq_cell->setPort("\\A", sig);
- eq_cell->setPort("\\B", comp);
- eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
+ eq_cell->setPort(ID::A, sig);
+ eq_cell->setPort(ID::B, comp);
+ eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
}
}
any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- any_cell->setPort("\\A", cmp_wire);
- any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire));
+ any_cell->setPort(ID::A, cmp_wire);
+ any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
}
return RTLIL::SigSpec(ctrl_wire);
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
- mux_cell->setPort("\\A", else_signal);
- mux_cell->setPort("\\B", when_signal);
- mux_cell->setPort("\\S", ctrl_sig);
- mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire));
+ mux_cell->setPort(ID::A, else_signal);
+ mux_cell->setPort(ID::B, when_signal);
+ mux_cell->setPort(ID::S, ctrl_sig);
+ mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
last_mux_cell = mux_cell;
return RTLIL::SigSpec(result_wire);
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
- log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
+ log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
- if (when_signal == last_mux_cell->getPort("\\A"))
+ if (when_signal == last_mux_cell->getPort(ID::A))
return;
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = "$pmux";
- RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S");
+ RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
new_s.append(ctrl_sig);
- last_mux_cell->setPort("\\S", new_s);
+ last_mux_cell->setPort(ID::S, new_s);
- RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B");
+ RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
new_b.append(when_signal);
- last_mux_cell->setPort("\\B", new_b);
+ last_mux_cell->setPort(ID::B, new_b);
- last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
+ last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort(ID::S).size();
}
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
{
pool<SigBit> bits;
- if (sw->get_bool_attribute("\\full_case"))
+ if (sw->get_bool_attribute(ID::full_case))
{
bool first_case = true;
std::vector<int> pgroups(sw->cases.size());
bool is_simple_parallel_case = true;
- if (!sw->get_bool_attribute("\\parallel_case")) {
+ if (!sw->get_bool_attribute(ID::parallel_case)) {
if (!swpara.count(sw)) {
pool<Const> case_values;
for (size_t i = 0; i < sw->cases.size(); i++) {
pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected)
{
pool<RTLIL::SigBit> all_assigned;
- bool full_case = sw->get_bool_attribute("\\full_case");
+ bool full_case = sw->get_bool_attribute(ID::full_case);
bool first = true;
for (auto it : sw->cases) {
if (it->compare.empty())
pool.take_all();
}
- if (pool.empty() && !sw->get_bool_attribute("\\full_case")) {
- sw->set_bool_attribute("\\full_case");
+ if (pool.empty() && !sw->get_bool_attribute(ID::full_case)) {
+ sw->set_bool_attribute(ID::full_case);
full_case_counter++;
}
}
int width = cell->getParam("\\WIDTH").as_int();
int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_s = sigmap(cell->getPort("\\S"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_s = sigmap(cell->getPort(ID::S));
for (int i = 0; i < numports; i++) {
SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width);
if (muxport_actsignal.count(muxport) == 0) {
if (portidx == 0)
- muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort("\\S"));
+ muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S));
else
- muxport_actsignal[muxport] = cell->getPort("\\S")[portidx-1];
+ muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1];
}
- output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort("\\Y")[bitidx])));
+ output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx])));
}
output.sort_and_unify();
int swidth = pmux->getParam("\\S_WIDTH").as_int();
int cntbits = ceil_log2(swidth+1);
- SigSpec sel = pmux->getPort("\\S");
+ SigSpec sel = pmux->getPort(ID::S);
SigSpec cnt(State::S0, cntbits);
for (int i = 0; i < swidth; i++)
assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID)));
if (!flag_always)
- assert_en.append(get_activation(pmux->getPort("\\Y")));
+ assert_en.append(get_activation(pmux->getPort(ID::Y)));
if (GetSize(assert_en) == 0)
assert_en = State::S1;
Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en);
- if (pmux->attributes.count("\\src") != 0)
- assert_cell->attributes["\\src"] = pmux->attributes.at("\\src");
+ if (pmux->attributes.count(ID::src) != 0)
+ assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src);
}
};
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
{
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
- SigSpec setval = cell->getPort("\\S");
+ SigSpec setval = cell->getPort(ID::S);
SigSpec clrval = cell->getPort("\\R");
if (cell->type[9] != 'P')
c->parameters["\\A_SIGNED"] = 0;
c->parameters["\\A_WIDTH"] = 1;
c->parameters["\\Y_WIDTH"] = 1;
- c->setPort("\\A", info.sig_clk);
- c->setPort("\\Y", wire_c);
+ c->setPort(ID::A, info.sig_clk);
+ c->setPort(ID::Y, wire_c);
}
if (info.sig_arst != RTLIL::State::Sm)
c->parameters["\\A_SIGNED"] = 0;
c->parameters["\\A_WIDTH"] = 1;
c->parameters["\\Y_WIDTH"] = 1;
- c->setPort("\\A", info.sig_arst);
- c->setPort("\\Y", wire_r);
+ c->setPort(ID::A, info.sig_arst);
+ c->setPort(ID::Y, wire_r);
}
RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
cell->attributes = gold_cell->attributes;
- cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src"));
+ cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src));
log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && cell->type == "$_NOT_")
- inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
+ if (inv_mode && cell->type == ID($_NOT_))
+ inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y))));
}
int bits_count = 0;
inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
- inv_cell->setPort("\\A", grp[0].bit);
- inv_cell->setPort("\\Y", inv_sig);
+ inv_cell->setPort(ID::A, grp[0].bit);
+ inv_cell->setPort(ID::Y, inv_sig);
}
module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
- eqx_cell->setPort("\\A", RTLIL::SigSpec(w_gold, i));
- eqx_cell->setPort("\\B", RTLIL::State::Sx);
- eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
+ eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i));
+ eqx_cell->setPort(ID::B, RTLIL::State::Sx);
+ eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
}
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width;
or_gold_cell->parameters["\\A_SIGNED"] = 0;
or_gold_cell->parameters["\\B_SIGNED"] = 0;
- or_gold_cell->setPort("\\A", w_gold);
- or_gold_cell->setPort("\\B", gold_x);
- or_gold_cell->setPort("\\Y", gold_masked);
+ or_gold_cell->setPort(ID::A, w_gold);
+ or_gold_cell->setPort(ID::B, gold_x);
+ or_gold_cell->setPort(ID::Y, gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width;
or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width;
or_gate_cell->parameters["\\A_SIGNED"] = 0;
or_gate_cell->parameters["\\B_SIGNED"] = 0;
- or_gate_cell->setPort("\\A", w_gate);
- or_gate_cell->setPort("\\B", gold_x);
- or_gate_cell->setPort("\\Y", gate_masked);
+ or_gate_cell->setPort(ID::A, w_gate);
+ or_gate_cell->setPort(ID::B, gold_x);
+ or_gate_cell->setPort(ID::Y, gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
- eq_cell->setPort("\\A", gold_masked);
- eq_cell->setPort("\\B", gate_masked);
- eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
- this_condition = eq_cell->getPort("\\Y");
+ eq_cell->setPort(ID::A, gold_masked);
+ eq_cell->setPort(ID::B, gate_masked);
+ eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+ this_condition = eq_cell->getPort(ID::Y);
}
else
{
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
- eq_cell->setPort("\\A", w_gold);
- eq_cell->setPort("\\B", w_gate);
- eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
- this_condition = eq_cell->getPort("\\Y");
+ eq_cell->setPort(ID::A, w_gold);
+ eq_cell->setPort(ID::B, w_gate);
+ eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+ this_condition = eq_cell->getPort(ID::Y);
}
if (flag_make_outcmp)
reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
reduce_cell->parameters["\\Y_WIDTH"] = 1;
reduce_cell->parameters["\\A_SIGNED"] = 0;
- reduce_cell->setPort("\\A", all_conditions);
- reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
- all_conditions = reduce_cell->getPort("\\Y");
+ reduce_cell->setPort(ID::A, all_conditions);
+ reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+ all_conditions = reduce_cell->getPort(ID::Y);
}
if (flag_make_assert) {
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
- assert_cell->setPort("\\A", all_conditions);
+ assert_cell->setPort(ID::A, all_conditions);
assert_cell->setPort("\\EN", State::S1);
}
not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
not_cell->parameters["\\A_SIGNED"] = 0;
- not_cell->setPort("\\A", all_conditions);
- not_cell->setPort("\\Y", w_trigger);
+ not_cell->setPort(ID::A, all_conditions);
+ not_cell->setPort(ID::Y, w_trigger);
miter_module->fixup_ports();
if (!cell->type.in("$assert", "$assume"))
continue;
- SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
+ SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
if (cell->type == "$assert") {
dict<SigBit, int> bit_user_cnt;
for (auto wire : module->wires()) {
- if (wire->name[0] == '\\' && wire->attributes.count("\\src"))
+ if (wire->name[0] == '\\' && wire->attributes.count(ID::src))
sigmap.add(wire);
}
entry.port = conn.first;
entry.portbit = i;
- for (auto &s : cell->get_strpool_attribute("\\src"))
+ for (auto &s : cell->get_strpool_attribute(ID::src))
entry.src.insert(s);
SigBit bit = sigmap(conn.second[i]);
if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
- for (auto &s : bit.wire->get_strpool_attribute("\\src"))
+ for (auto &s : bit.wire->get_strpool_attribute(ID::src))
entry.src.insert(s);
entry.wire = bit.wire->name;
entry.wirebit = bit.offset;
strftime(stime, sizeof(stime), "%c", now);
std::string module_fname = "unknown";
- auto apos = module->attributes.find("\\src");
+ auto apos = module->attributes.find(ID::src);
if(apos != module->attributes.end())
- module_fname = module->attributes["\\src"].decode_string();
+ module_fname = module->attributes[ID::src].decode_string();
fprintf(f, "$date\n");
fprintf(f, " %s\n", stime);
RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
bool has_a, has_b, has_c, has_d, has_s, has_y;
- has_a = cell->hasPort("\\A");
- has_b = cell->hasPort("\\B");
+ has_a = cell->hasPort(ID::A);
+ has_b = cell->hasPort(ID::B);
has_c = cell->hasPort("\\C");
has_d = cell->hasPort("\\D");
- has_s = cell->hasPort("\\S");
- has_y = cell->hasPort("\\Y");
+ has_s = cell->hasPort(ID::S);
+ has_y = cell->hasPort(ID::Y);
- if (has_a) sig_a = cell->getPort("\\A");
- if (has_b) sig_b = cell->getPort("\\B");
+ if (has_a) sig_a = cell->getPort(ID::A);
+ if (has_b) sig_b = cell->getPort(ID::B);
if (has_c) sig_c = cell->getPort("\\C");
if (has_d) sig_d = cell->getPort("\\D");
- if (has_s) sig_s = cell->getPort("\\S");
- if (has_y) sig_y = cell->getPort("\\Y");
+ if (has_s) sig_s = cell->getPort(ID::S);
+ if (has_y) sig_y = cell->getPort(ID::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
for (auto cell : formal_database)
{
string label = log_id(cell);
- if (cell->attributes.count("\\src"))
- label = cell->attributes.at("\\src").decode_string();
+ if (cell->attributes.count(ID::src))
+ label = cell->attributes.at(ID::src).decode_string();
- State a = get_state(cell->getPort("\\A"))[0];
+ State a = get_state(cell->getPort(ID::A))[0];
State en = get_state(cell->getPort("\\EN"))[0];
if (cell->type == "$cover" && en == State::S1 && a != State::S1)
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
+ IdString clkbuf_inhibit("\\clkbuf_inhibit");
+
// Process submodules before module using them.
std::vector<Module *> modules_sorted;
pool<Module *> modules_processed;
if (wire->port_input && wire->port_output)
continue;
bool process_wire = module->selected(wire);
- if (!select && wire->get_bool_attribute("\\clkbuf_inhibit"))
+ if (!select && wire->get_bool_attribute(clkbuf_inhibit))
process_wire = false;
if (!process_wire) {
// This wire is supposed to be bypassed, so make sure we don't buffer it in
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
} else if (!sink_wire_bits.count(mapped_wire_bit)) {
// Nothing to do.
- } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) {
+ } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) {
// Clock network not yet buffered, driven by one of
// our cells or a top-level input -- buffer it.
Wire *iwire = module->addWire(NEW_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
- if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) {
+ if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top)) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
- std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y";
+ IdString celltype = "$_BUF_", in_portname = ID::A, out_portname = ID::Y;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
std::string arg = args[argidx];
if (arg == "-buf" && argidx+3 < args.size()) {
- celltype = args[++argidx];
- in_portname = args[++argidx];
- out_portname = args[++argidx];
+ celltype = RTLIL::escape_id(args[++argidx]);
+ in_portname = RTLIL::escape_id(args[++argidx]);
+ out_portname = RTLIL::escape_id(args[++argidx]);
continue;
}
break;
continue;
}
- Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
- cell->setPort(RTLIL::escape_id(in_portname), rhs);
- cell->setPort(RTLIL::escape_id(out_portname), lhs);
+ Cell *cell = module->addCell(NEW_ID, celltype);
+ cell->setPort(in_portname, rhs);
+ cell->setPort(out_portname, lhs);
log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
}
int width = 1 + xorshift32(8);
int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
- wire = module->addWire("\\A");
+ wire = module->addWire(ID::A);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\A", wire);
+ cell->setPort(ID::A, wire);
- wire = module->addWire("\\B");
+ wire = module->addWire(ID::B);
wire->width = width * swidth;
wire->port_input = true;
- cell->setPort("\\B", wire);
+ cell->setPort(ID::B, wire);
- wire = module->addWire("\\S");
+ wire = module->addWire(ID::S);
wire->width = swidth;
wire->port_input = true;
- cell->setPort("\\S", wire);
+ cell->setPort(ID::S, wire);
- wire = module->addWire("\\Y");
+ wire = module->addWire(ID::Y);
wire->width = width;
wire->port_output = true;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
}
if (cell_type == "$fa")
{
int width = 1 + xorshift32(8);
- wire = module->addWire("\\A");
+ wire = module->addWire(ID::A);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\A", wire);
+ cell->setPort(ID::A, wire);
- wire = module->addWire("\\B");
+ wire = module->addWire(ID::B);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\B", wire);
+ cell->setPort(ID::B, wire);
wire = module->addWire("\\C");
wire->width = width;
wire->port_output = true;
cell->setPort("\\X", wire);
- wire = module->addWire("\\Y");
+ wire = module->addWire(ID::Y);
wire->width = width;
wire->port_output = true;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
}
if (cell_type == "$lcu")
int depth = 1 + xorshift32(6);
int mulbits_a = 0, mulbits_b = 0;
- RTLIL::Wire *wire_a = module->addWire("\\A");
+ RTLIL::Wire *wire_a = module->addWire(ID::A);
wire_a->width = 0;
wire_a->port_input = true;
macc.ports.push_back(this_port);
}
- wire = module->addWire("\\B");
+ wire = module->addWire(ID::B);
wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1);
wire->port_input = true;
macc.bit_ports = wire;
- wire = module->addWire("\\Y");
+ wire = module->addWire(ID::Y);
wire->width = width;
wire->port_output = true;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
macc.to_cell(cell);
}
{
int width = 1 + xorshift32(6);
- wire = module->addWire("\\A");
+ wire = module->addWire(ID::A);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\A", wire);
+ cell->setPort(ID::A, wire);
- wire = module->addWire("\\Y");
+ wire = module->addWire(ID::Y);
wire->port_output = true;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
RTLIL::SigSpec config;
for (int i = 0; i < (1 << width); i++)
int width = 1 + xorshift32(8);
int depth = 1 + xorshift32(8);
- wire = module->addWire("\\A");
+ wire = module->addWire(ID::A);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\A", wire);
+ cell->setPort(ID::A, wire);
- wire = module->addWire("\\Y");
+ wire = module->addWire(ID::Y);
wire->port_output = true;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
RTLIL::SigSpec config;
for (int i = 0; i < width*depth; i++)
}
if (cell_type_flags.find('A') != std::string::npos) {
- wire = module->addWire("\\A");
+ wire = module->addWire(ID::A);
wire->width = 1 + xorshift32(8);
wire->port_input = true;
- cell->setPort("\\A", wire);
+ cell->setPort(ID::A, wire);
}
if (cell_type_flags.find('B') != std::string::npos) {
- wire = module->addWire("\\B");
+ wire = module->addWire(ID::B);
if (cell_type_flags.find('h') != std::string::npos)
wire->width = 1 + xorshift32(6);
else
wire->width = 1 + xorshift32(8);
wire->port_input = true;
- cell->setPort("\\B", wire);
+ cell->setPort(ID::B, wire);
}
if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
}
if (cell_type_flags.find('Y') != std::string::npos) {
- wire = module->addWire("\\Y");
+ wire = module->addWire(ID::Y);
wire->width = 1 + xorshift32(8);
wire->port_output = true;
- cell->setPort("\\Y", wire);
+ cell->setPort(ID::Y, wire);
}
if (muxdiv && cell_type.in("$div", "$mod")) {
- auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B"));
- auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y")));
- module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y"));
- cell->setPort("\\Y", div_out);
+ auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
+ auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));
+ module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
+ cell->setPort(ID::Y, div_out);
}
if (cell_type == "$alu")
cell->setPort("\\BI", wire);
wire = module->addWire("\\X");
- wire->width = GetSize(cell->getPort("\\Y"));
+ wire->width = GetSize(cell->getPort(ID::Y));
wire->port_output = true;
cell->setPort("\\X", wire);
wire = module->addWire("\\CO");
- wire->width = GetSize(cell->getPort("\\Y"));
+ wire->width = GetSize(cell->getPort(ID::Y));
wire->port_output = true;
cell->setPort("\\CO", wire);
}
{
if (cell->type == "$_NOT_")
{
- auto not_input = sigmap(cell->getPort("\\A")[0]);
- auto not_output = sigmap(cell->getPort("\\Y")[0]);
+ auto not_input = sigmap(cell->getPort(ID::A)[0]);
+ auto not_output = sigmap(cell->getPort(ID::Y)[0]);
not_cells[not_input] = tuple<SigBit, Cell*>(not_output, cell);
}
}
if (cell->type == "$sop")
{
// Read the inputs/outputs/parameters of the $sop cell
- auto sop_inputs = sigmap(cell->getPort("\\A"));
- auto sop_output = sigmap(cell->getPort("\\Y"))[0];
+ auto sop_inputs = sigmap(cell->getPort(ID::A));
+ auto sop_output = sigmap(cell->getPort(ID::Y))[0];
auto sop_depth = cell->getParam("\\DEPTH").as_int();
auto sop_width = cell->getParam("\\WIDTH").as_int();
auto sop_table = cell->getParam("\\TABLE");
if (type_str.back() == 'S') {
type_str.back() = 'R';
cell->type = type_str;
- cell->setPort("\\R", cell->getPort("\\S"));
- cell->unsetPort("\\S");
+ cell->setPort("\\R", cell->getPort(ID::S));
+ cell->unsetPort(ID::S);
} else
if (type_str.back() == 'R') {
type_str.back() = 'S';
cell->type = type_str;
- cell->setPort("\\S", cell->getPort("\\R"));
+ cell->setPort(ID::S, cell->getPort("\\R"));
cell->unsetPort("\\R");
}
if (cell->type != "$_MUX_")
continue;
- SigBit bit_a = sigmap(cell->getPort("\\A"));
- SigBit bit_b = sigmap(cell->getPort("\\B"));
+ SigBit bit_a = sigmap(cell->getPort(ID::A));
+ SigBit bit_b = sigmap(cell->getPort(ID::B));
if (bit_a.wire == nullptr || bit_b.wire == nullptr)
- sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
+ sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
}
for (auto cell : ff_cells)
continue;
Cell *mux_cell = sr_muxes.at(bit_d);
- SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
- SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
- SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
+ SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
+ SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
+ SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
if (sr_val == State::S1) {
cell->type = cell->type.str() + "SS";
- cell->setPort("\\S", sr_sig);
+ cell->setPort(ID::S, sr_sig);
cell->setPort("\\D", bit_d);
} else {
cell->type = cell->type.str() + "SR";
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
- cell->getPort("\\A"),
- cell->getPort("\\B"),
+ cell->getPort(ID::A),
+ cell->getPort(ID::B),
cell->getPort("\\CI")
};
for (int i = 0; i < 3; i++)
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
- cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
- cell->setPort("\\Y", cell->getPort("\\O"));
- cell->unsetPort("\\B");
+ cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
+ cell->setPort(ID::Y, cell->getPort("\\O"));
+ cell->unsetPort(ID::B);
cell->unsetPort("\\CI");
cell->unsetPort("\\I0");
cell->unsetPort("\\I3");
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
- cell->setPort("\\A", SigSpec({
+ cell->setPort(ID::A, SigSpec({
get_bit_or_zero(cell->getPort("\\I3")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0"))
}));
- cell->setPort("\\Y", cell->getPort("\\O")[0]);
+ cell->setPort(ID::Y, cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");
buf_port = "\\D";
} else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
buf_type = "\\CLKBUF";
- buf_port = "\\Y";
+ buf_port = ID::Y;
} else {
buf_type = "\\INBUF";
- buf_port = "\\Y";
+ buf_port = ID::Y;
}
Cell *c = module->addCell(NEW_ID, buf_type);
}
if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF",
"\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) {
- for (auto bit : sigmap(cell->getPort("\\Y")))
+ for (auto bit : sigmap(cell->getPort(ID::Y)))
handled_clk_bits.push_back(bit);
}
}
if (clk_bits.count(canonical_bit)) {
Cell *c = module->addCell(NEW_ID, "\\CLKINT");
SigBit new_bit = module->addWire(NEW_ID);
- c->setPort("\\A", new_bit);
- c->setPort("\\Y", bit);
+ c->setPort(ID::A, new_bit);
+ c->setPort(ID::Y, bit);
log("Added %s cell %s for clock signal %s.\n", log_id(c->type), log_id(c), log_signal(bit));
clk_bits.erase(canonical_bit);
did_something = true;
projects / yosys.git / commitdiff