It appears that we can't do this in a single command (like we do for
MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about
the command length if I try to combine them. No matter.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
uint32_t reg, uint64_t imm);
void brw_load_register_reg(struct brw_context *brw, uint32_t src,
uint32_t dest);
+void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
+ uint32_t dest);
void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
uint32_t offset, uint32_t imm);
void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
ADVANCE_BATCH();
}
+/*
+ * Copies a 64-bit register.
+ */
+void
+brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
+{
+ assert(brw->gen >= 8 || brw->is_haswell);
+
+ BEGIN_BATCH(6);
+ OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
+ OUT_BATCH(src);
+ OUT_BATCH(dest);
+ OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
+ OUT_BATCH(src + sizeof(uint32_t));
+ OUT_BATCH(dest + sizeof(uint32_t));
+ ADVANCE_BATCH();
+}
+
/*
* Write 32-bits of immediate data to a GPU memory buffer.
*/