re PR target/65249 (unable to find a register to spill in class 'R0_REGS' when compil...

PR target/65249
* config/sh/sh.md (movdi): Split simple reg move to two movsi when
  the destination is R0 so as to lower R0-register pressure.

From-SVN: r225856

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6f5459d47972fb1aaf022a4af9153354a95d009a..603c5e3a1e4a33b33e8f1d245725b5386dc12439 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-07-16  Kaz Kojima  <kkojima@gcc.gnu.org>
+
+       PR target/65249
+       * config/sh/sh.md (movdi): Split simple reg move to two movsi
+       when the destination is R0.
+
 2015-07-16  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/66866

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index f0cb3cfe8c4e227532c00035db78b80deb6c44d2..61f663778d0a9d3fca1da9f6ca3376832dff610e 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -7892,6 +7892,24 @@ label:
   ""
 {
   prepare_move_operands (operands, DImode);
+  if (TARGET_SH1)
+    {
+      /* When the dest operand is (R0, R1) register pair, split it to
+        two movsi of which dest is R1 and R0 so as to lower R0-register
+        pressure on the first movsi.  Apply only for simple source not
+        to make complex rtl here.  */
+      if (REG_P (operands[0])
+         && REGNO (operands[0]) == R0_REG
+         && REG_P (operands[1])
+         && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
+       {
+         emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
+                               gen_rtx_SUBREG (SImode, operands[1], 4)));
+         emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
+                               gen_rtx_SUBREG (SImode, operands[1], 0)));
+         DONE;
+       }
+    }
 })
 
 (define_insn "movdf_media"