return design;
 
                RTLIL::Design *design_copy = new RTLIL::Design;
-               for (auto &it : design->modules_)
-                       design_copy->add(it.second->clone());
+               for (auto module : design->modules())
+                       design_copy->add(module->clone());
                Pass::call(design_copy, "proc_clean -quiet");
                Pass::call(design_copy, "clean -purge");
 
        RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool assigns, bool updates)
        {
                RTLIL::Design *design_copy = new RTLIL::Design;
-               for (auto &it : design->modules_)
-                       design_copy->add(it.second->clone());
+               for (auto module : design->modules())
+                       design_copy->add(module->clone());
 
                int index = 0;
                if (modules)
                {
-                       for (auto &it : design_copy->modules_)
+                       for (auto module : design_copy->modules())
                        {
-                               if (it.second->get_blackbox_attribute())
+                               if (module->get_blackbox_attribute())
                                        continue;
 
                                if (index++ == seed)
                                {
-                                       log("Trying to remove module %s.\n", it.first.c_str());
-                                       design_copy->remove(it.second);
+                                       log("Trying to remove module %s.\n", module->name.c_str());
+                                       design_copy->remove(module);
                                        return design_copy;
                                }
                        }
                                if (mod->get_blackbox_attribute())
                                        continue;
 
-                               for (auto &it : mod->cells_)
+                               for (auto cell : mod->cells())
                                {
                                        if (index++ == seed)
                                        {
-                                               log("Trying to remove cell %s.%s.\n", mod->name.c_str(), it.first.c_str());
-                                               mod->remove(it.second);
+                                               log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str());
+                                               mod->remove(cell);
                                                return design_copy;
                                        }
                                }
                                }
                        }
                }
-               return NULL;
+               return nullptr;
        }
 
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
                {
                        Pass::call(design, "design -reset");
                        crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
-                       for (auto &it : crashing_design->modules_)
-                               design->add(it.second->clone());
+                       for (auto module : crashing_design->modules())
+                               design->add(module->clone());
                        delete crashing_design;
                }
        }