tools/flterm
tools/mkmmimg
tools/byteswap
+software/include/hw/csr.h
#!/usr/bin/env python3
import os
+
from mibuild.platforms import m1
+from mibuild.tools import write_to_file
+
import top
+import cif
def main():
plat = m1.Platform()
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
-
+
plat.build_cmdline(soc)
+ csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
+ write_to_file("software/include/hw/csr.h", csr_header)
if __name__ == "__main__":
main()
--- /dev/null
+from operator import itemgetter
+import re
+
+def get_macros(filename):
+ f = open(filename, "r")
+ r = {}
+ for line in f:
+ match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
+ if match:
+ r[match.group(1)] = match.group(2)
+ return r
+
+def _get_rw_functions(reg_name, reg_base, size):
+ r = ""
+ if size > 8:
+ raise NotImplementedError("Register too large")
+ elif size > 4:
+ ctype = "unsigned long long int"
+ elif size > 2:
+ ctype = "unsigned int"
+ elif size > 1:
+ ctype = "unsigned short int"
+ else:
+ ctype = "unsigned char"
+
+ r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
+ if size > 1:
+ r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
+ for byte in range(1, size):
+ r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
+ r += "\treturn r;\n}\n"
+ else:
+ r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
+
+ r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
+ for byte in range(size):
+ shift = (size-byte-1)*8
+ if shift:
+ value_shifted = "value >> "+str(shift)
+ else:
+ value_shifted = "value"
+ r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
+ r += "}\n"
+ return r
+
+def get_csr_header(csr_base, bank_array, interrupt_map):
+ r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
+ for name, rmap in bank_array.banks:
+ r += "\n/* "+name+" */\n"
+ reg_base = csr_base + 0x800*rmap.address
+ r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
+ for register in rmap.description:
+ nr = (register.get_size() + 7)//8
+ r += _get_rw_functions(name + "_" + register.name, reg_base, nr)
+ reg_base += 4*nr
+ try:
+ interrupt_nr = interrupt_map[name]
+ except KeyError:
+ pass
+ else:
+ r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
+ r += "\n#endif\n"
+ return r
+++ /dev/null
-import re
-
-def get_macros(filename):
- f = open(filename, "r")
- r = {}
- for line in f:
- match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
- if match:
- r[match.group(1)] = match.group(2)
- return r
+++ /dev/null
-#ifndef __CSRBASE_H
-#define __CSRBASE_H
-
-#define UART_BASE 0xe0000000
-#define DFII_BASE 0xe0000800
-#define IDENTIFIER_BASE 0xe0001000
-#define TIMER0_BASE 0xe0001800
-#define MINIMAC_BASE 0xe0002000
-#define FB_BASE 0xe0002800
-#define ASMIPROBE_BASE 0xe0003000
-#define DVISAMPLER0_BASE 0xe0003800
-#define DVISAMPLER0_EDID_MEM_BASE 0xe0004000
-#define DVISAMPLER1_BASE 0xe0004800
-#define DVISAMPLER1_EDID_MEM_BASE 0xe0005000
-
-#endif /* __CSRBASE_H */
+++ /dev/null
-#ifndef __INTERRUPT_H
-#define __INTERRUPT_H
-
-#define UART_INTERRUPT 0
-#define TIMER0_INTERRUPT 1
-#define MINIMAC_INTERRUPT 2
-
-#endif /* __INTERRUPT_H */
-#include <hw/uart.h>
-#include <interrupt.h>
+#include <hw/csr.h>
#include <irq.h>
#include <uart.h>
#include <timer.h>
#include <hw/mem.h>
-#include <hw/minimac.h>
#include "sdram.h"
#include "dataflow.h"
#include "boot.h"
+#include "microudp.h"
enum {
CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA,
}
}
-static void ethreset(void)
-{
- CSR_MINIMAC_PHYRST = 0;
- busy_wait(2);
- /* that pesky ethernet PHY needs two resets at times... */
- CSR_MINIMAC_PHYRST = 1;
- busy_wait(2);
- CSR_MINIMAC_PHYRST = 0;
- busy_wait(2);
-}
-
static void print_mac(void)
{
unsigned char *macadr = (unsigned char *)FLASH_OFFSET_MAC_ADDRESS;
#include <stdio.h>
#include <system.h>
#include <crc.h>
-#include <hw/minimac.h>
+#include <timer.h>
+#include <hw/csr.h>
+#include <hw/flags.h>
+#include <hw/mem.h>
#include "microudp.h"
} ethernet_buffer;
-static int rxlen;
+static unsigned int rxlen;
static ethernet_buffer *rxbuffer;
static ethernet_buffer *rxbuffer0;
static ethernet_buffer *rxbuffer1;
-static int txlen;
+static unsigned int txlen;
static ethernet_buffer *txbuffer;
static void send_packet(void)
txbuffer->raw[txlen+2] = (crc & 0xff0000) >> 16;
txbuffer->raw[txlen+3] = (crc & 0xff000000) >> 24;
txlen += 4;
- CSR_MINIMAC_TXCOUNTH = (txlen & 0xff00) >> 8;
- CSR_MINIMAC_TXCOUNTL = txlen & 0x00ff;
- CSR_MINIMAC_TXSTART = 1;
- while(!(CSR_MINIMAC_EV_PENDING & MINIMAC_EV_TX));
- CSR_MINIMAC_EV_PENDING = MINIMAC_EV_TX;
+ minimac_tx_count_write(txlen);
+ minimac_tx_start_write(1);
+ while(!(minimac_ev_pending_read() & MINIMAC_EV_TX));
+ minimac_ev_pending_write(MINIMAC_EV_TX);
}
static unsigned char my_mac[6];
static unsigned short ip_checksum(unsigned int r, void *buffer, unsigned int length, int complete)
{
unsigned char *ptr;
- int i;
+ unsigned int i;
ptr = (unsigned char *)buffer;
length >>= 1;
{
int i;
- CSR_MINIMAC_EV_PENDING = MINIMAC_EV_RX0 | MINIMAC_EV_RX1 | MINIMAC_EV_TX;
+ minimac_ev_pending_write(MINIMAC_EV_RX0 | MINIMAC_EV_RX1 | MINIMAC_EV_TX);
rxbuffer0 = (ethernet_buffer *)MINIMAC_RX0_BASE;
rxbuffer1 = (ethernet_buffer *)MINIMAC_RX1_BASE;
void microudp_service(void)
{
- if(CSR_MINIMAC_EV_PENDING & MINIMAC_EV_RX0) {
- rxlen = (CSR_MINIMAC_RXCOUNT0H << 8) | CSR_MINIMAC_RXCOUNT0L;
+ if(minimac_ev_pending_read() & MINIMAC_EV_RX0) {
+ rxlen = minimac_rx_count_0_read();
rxbuffer = rxbuffer0;
process_frame();
- CSR_MINIMAC_EV_PENDING = MINIMAC_EV_RX0;
+ minimac_ev_pending_write(MINIMAC_EV_RX0);
}
- if(CSR_MINIMAC_EV_PENDING & MINIMAC_EV_RX1) {
- rxlen = (CSR_MINIMAC_RXCOUNT1H << 8) | CSR_MINIMAC_RXCOUNT1L;
+ if(minimac_ev_pending_read() & MINIMAC_EV_RX1) {
+ rxlen = minimac_rx_count_1_read();
rxbuffer = rxbuffer1;
process_frame();
- CSR_MINIMAC_EV_PENDING = MINIMAC_EV_RX1;
+ minimac_ev_pending_write(MINIMAC_EV_RX1);
}
}
+
+void ethreset(void)
+{
+ minimac_phy_reset_write(0);
+ busy_wait(2);
+ /* that pesky ethernet PHY needs two resets at times... */
+ minimac_phy_reset_write(1);
+ busy_wait(2);
+ minimac_phy_reset_write(0);
+ busy_wait(2);
+}
void microudp_set_callback(udp_callback callback);
void microudp_service(void);
+void ethreset(void);
+
#endif /* __MICROUDP_H */
#include <stdio.h>
#include <stdlib.h>
-#include <hw/dfii.h>
+#include <hw/csr.h>
+#include <hw/flags.h>
#include <hw/mem.h>
-#include <csrbase.h>
#include "sdram.h"
}
}
-static void setaddr(int a)
-{
- CSR_DFII_AH_P0 = (a & 0xff00) >> 8;
- CSR_DFII_AL_P0 = a & 0x00ff;
- CSR_DFII_AH_P1 = (a & 0xff00) >> 8;
- CSR_DFII_AL_P1 = a & 0x00ff;
-}
-
static void command_p0(int cmd)
{
- CSR_DFII_COMMAND_P0 = cmd;
- CSR_DFII_COMMAND_ISSUE_P0 = 1;
+ dfii_pi0_command_write(cmd);
+ dfii_pi0_command_issue_write(1);
}
static void command_p1(int cmd)
{
- CSR_DFII_COMMAND_P1 = cmd;
- CSR_DFII_COMMAND_ISSUE_P1 = 1;
+ dfii_pi1_command_write(cmd);
+ dfii_pi1_command_issue_write(1);
}
static void init_sequence(void)
int i;
/* Bring CKE high */
- setaddr(0x0000);
- CSR_DFII_BA_P0 = 0;
- CSR_DFII_CONTROL = DFII_CONTROL_CKE;
+ dfii_pi0_address_write(0x0000);
+ dfii_pi0_baddress_write(0);
+ dfii_control_write(DFII_CONTROL_CKE);
/* Precharge All */
- setaddr(0x0400);
+ dfii_pi0_address_write(0x0400);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Extended Mode Register */
- CSR_DFII_BA_P0 = 1;
- setaddr(0x0000);
+ dfii_pi0_baddress_write(1);
+ dfii_pi0_address_write(0x0000);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
- CSR_DFII_BA_P0 = 0;
+ dfii_pi0_baddress_write(0);
/* Load Mode Register */
- setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
+ dfii_pi0_address_write(0x0132); /* Reset DLL, CL=3, BL=4 */
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* Precharge All */
- setaddr(0x0400);
+ dfii_pi0_address_write(0x0400);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* 2x Auto Refresh */
for(i=0;i<2;i++) {
- setaddr(0);
+ dfii_pi0_address_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4);
}
/* Load Mode Register */
- setaddr(0x0032); /* CL=3, BL=4 */
+ dfii_pi0_address_write(0x0032); /* CL=3, BL=4 */
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
void ddrsw(void)
{
- CSR_DFII_CONTROL = DFII_CONTROL_CKE;
+ dfii_control_write(DFII_CONTROL_CKE);
printf("DDR now under software control\n");
}
void ddrhw(void)
{
- CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
+ dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
printf("DDR now under hardware control\n");
}
unsigned int row;
if(*_row == 0) {
- setaddr(0x0000);
- CSR_DFII_BA_P0 = 0;
+ dfii_pi0_address_write(0x0000);
+ dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(15);
printf("Precharged\n");
printf("incorrect row\n");
return;
}
- setaddr(row);
- CSR_DFII_BA_P0 = 0;
+ dfii_pi0_address_write(row);
+ dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
cdelay(15);
printf("Activated row %d\n", row);
return;
}
- setaddr(addr);
- CSR_DFII_BA_P0 = 0;
+ dfii_pi0_address_write(addr);
+ dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15);
MMPTR(0xe0000864+4*i) = 0xf0 + i;
}
- setaddr(addr);
- CSR_DFII_BA_P1 = 0;
+ dfii_pi1_address_write(addr);
+ dfii_pi1_baddress_write(0);
command_p1(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
}
printf("Initializing DDR SDRAM...\n");
init_sequence();
- CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
+ dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
if(!memtest())
return 0;
+++ /dev/null
-#ifndef __HW_DFII_H
-#define __HW_DFII_H
-
-#include <hw/common.h>
-#include <csrbase.h>
-
-#define DFII_CSR(x) MMPTR(DFII_BASE+(x))
-
-#define CSR_DFII_CONTROL DFII_CSR(0x00)
-
-#define DFII_CONTROL_SEL 0x01
-#define DFII_CONTROL_CKE 0x02
-
-#define CSR_DFII_COMMAND_P0 DFII_CSR(0x04)
-#define CSR_DFII_COMMAND_ISSUE_P0 DFII_CSR(0x08)
-#define CSR_DFII_AH_P0 DFII_CSR(0x0C)
-#define CSR_DFII_AL_P0 DFII_CSR(0x10)
-#define CSR_DFII_BA_P0 DFII_CSR(0x14)
-#define CSR_DFII_WD0_P0 DFII_CSR(0x18)
-#define CSR_DFII_WD1_P0 DFII_CSR(0x1C)
-#define CSR_DFII_WD2_P0 DFII_CSR(0x20)
-#define CSR_DFII_WD3_P0 DFII_CSR(0x24)
-#define CSR_DFII_WD4_P0 DFII_CSR(0x28)
-#define CSR_DFII_WD5_P0 DFII_CSR(0x2C)
-#define CSR_DFII_WD6_P0 DFII_CSR(0x30)
-#define CSR_DFII_WD7_P0 DFII_CSR(0x34)
-#define CSR_DFII_RD0_P0 DFII_CSR(0x38)
-#define CSR_DFII_RD1_P0 DFII_CSR(0x3C)
-#define CSR_DFII_RD2_P0 DFII_CSR(0x40)
-#define CSR_DFII_RD3_P0 DFII_CSR(0x44)
-#define CSR_DFII_RD4_P0 DFII_CSR(0x48)
-#define CSR_DFII_RD5_P0 DFII_CSR(0x4C)
-#define CSR_DFII_RD6_P0 DFII_CSR(0x50)
-#define CSR_DFII_RD7_P0 DFII_CSR(0x54)
-
-#define CSR_DFII_COMMAND_P1 DFII_CSR(0x58)
-#define CSR_DFII_COMMAND_ISSUE_P1 DFII_CSR(0x5C)
-#define CSR_DFII_AH_P1 DFII_CSR(0x60)
-#define CSR_DFII_AL_P1 DFII_CSR(0x64)
-#define CSR_DFII_BA_P1 DFII_CSR(0x68)
-#define CSR_DFII_WD0_P1 DFII_CSR(0x6C)
-#define CSR_DFII_WD1_P1 DFII_CSR(0x70)
-#define CSR_DFII_WD2_P1 DFII_CSR(0x74)
-#define CSR_DFII_WD3_P1 DFII_CSR(0x78)
-#define CSR_DFII_WD4_P1 DFII_CSR(0x7C)
-#define CSR_DFII_WD5_P1 DFII_CSR(0x80)
-#define CSR_DFII_WD6_P1 DFII_CSR(0x84)
-#define CSR_DFII_WD7_P1 DFII_CSR(0x88)
-#define CSR_DFII_RD0_P1 DFII_CSR(0x8C)
-#define CSR_DFII_RD1_P1 DFII_CSR(0x90)
-#define CSR_DFII_RD2_P1 DFII_CSR(0x94)
-#define CSR_DFII_RD3_P1 DFII_CSR(0x98)
-#define CSR_DFII_RD4_P1 DFII_CSR(0x9C)
-#define CSR_DFII_RD5_P1 DFII_CSR(0xA0)
-#define CSR_DFII_RD6_P1 DFII_CSR(0xA4)
-#define CSR_DFII_RD7_P1 DFII_CSR(0xA8)
-
-#define DFII_COMMAND_CS 0x01
-#define DFII_COMMAND_WE 0x02
-#define DFII_COMMAND_CAS 0x04
-#define DFII_COMMAND_RAS 0x08
-#define DFII_COMMAND_WRDATA 0x10
-#define DFII_COMMAND_RDDATA 0x20
-
-#endif /* __HW_DFII_H */
+++ /dev/null
-#ifndef __HW_DVISAMPLER_H
-#define __HW_DVISAMPLER_H
-
-#include <hw/common.h>
-#include <csrbase.h>
-
-#define DVISAMPLER0_CSR(x) MMPTR(DVISAMPLER0_BASE+(x))
-
-#define CSR_DVISAMPLER0_PLL_RESET DVISAMPLER0_CSR(0x00)
-#define CSR_DVISAMPLER0_PLL_LOCKED DVISAMPLER0_CSR(0x04)
-
-#define CSR_DVISAMPLER0_D0_DELAY_CTL DVISAMPLER0_CSR(0x08)
-#define CSR_DVISAMPLER0_D0_DELAY_BUSY DVISAMPLER0_CSR(0x0C)
-#define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10)
-#define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14)
-#define CSR_DVISAMPLER0_D0_CHAR_SYNCED DVISAMPLER0_CSR(0x18)
-#define CSR_DVISAMPLER0_D0_CTL_POS DVISAMPLER0_CSR(0x1C)
-
-#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x20)
-#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x24)
-#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x28)
-#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x2C)
-#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x30)
-#define CSR_DVISAMPLER0_D1_CTL_POS DVISAMPLER0_CSR(0x34)
-
-#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x38)
-#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x3C)
-#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x40)
-#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x44)
-#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x48)
-#define CSR_DVISAMPLER0_D2_CTL_POS DVISAMPLER0_CSR(0x4C)
-
-#define CSR_DVISAMPLER0_CHAN_SYNCED DVISAMPLER0_CSR(0x50)
-
-#define CSR_DVISAMPLER0_HRESH DVISAMPLER0_CSR(0x54)
-#define CSR_DVISAMPLER0_HRESL DVISAMPLER0_CSR(0x58)
-#define CSR_DVISAMPLER0_VRESH DVISAMPLER0_CSR(0x5C)
-#define CSR_DVISAMPLER0_VRESL DVISAMPLER0_CSR(0x60)
-#define CSR_DVISAMPLER0_DECNT2 DVISAMPLER0_CSR(0x64)
-#define CSR_DVISAMPLER0_DECNT1 DVISAMPLER0_CSR(0x68)
-#define CSR_DVISAMPLER0_DECNT0 DVISAMPLER0_CSR(0x6C)
-
-#define DVISAMPLER_DELAY_CAL 0x01
-#define DVISAMPLER_DELAY_RST 0x02
-#define DVISAMPLER_DELAY_INC 0x04
-#define DVISAMPLER_DELAY_DEC 0x08
-
-#define DVISAMPLER_TOO_LATE 0x01
-#define DVISAMPLER_TOO_EARLY 0x02
-
-#endif /* __HW_DVISAMPLER_H */
--- /dev/null
+#ifndef __HW_FLAGS_H
+#define __HW_FLAGS_H
+
+#define UART_EV_TX 0x1
+#define UART_EV_RX 0x2
+
+#define DFII_CONTROL_SEL 0x01
+#define DFII_CONTROL_CKE 0x02
+
+#define DFII_COMMAND_CS 0x01
+#define DFII_COMMAND_WE 0x02
+#define DFII_COMMAND_CAS 0x04
+#define DFII_COMMAND_RAS 0x08
+#define DFII_COMMAND_WRDATA 0x10
+#define DFII_COMMAND_RDDATA 0x20
+
+#define MINIMAC_EV_RX0 0x1
+#define MINIMAC_EV_RX1 0x2
+#define MINIMAC_EV_TX 0x4
+
+#endif /* __HW_FLAGS_H */
+++ /dev/null
-#ifndef __HW_GPIO_H
-#define __HW_GPIO_H
-
-/* Inputs */
-#define GPIO_BTN1 (0x00000001)
-#define GPIO_BTN2 (0x00000002)
-#define GPIO_BTN3 (0x00000004)
-
-#define GPIO_PCBREV0 (0x00000008)
-#define GPIO_PCBREV1 (0x00000010)
-#define GPIO_PCBREV2 (0x00000020)
-#define GPIO_PCBREV3 (0x00000040)
-
-/* Outputs */
-#define GPIO_LED1 (0x00000001)
-#define GPIO_LED2 (0x00000002)
-
-#endif /* __HW_GPIO_H */
+++ /dev/null
-#ifndef __HW_IDENTIFIER_H
-#define __HW_IDENTIFIER_H
-
-#include <hw/common.h>
-#include <csrbase.h>
-
-#define IDENTIFIER_CSR(x) MMPTR(IDENTIFIER_BASE+(x))
-
-#define CSR_IDENTIFIER_SYSTEMH IDENTIFIER_CSR(0x00)
-#define CSR_IDENTIFIER_SYSTEML IDENTIFIER_CSR(0x04)
-#define CSR_IDENTIFIER_VERSIONH IDENTIFIER_CSR(0x08)
-#define CSR_IDENTIFIER_VERSIONL IDENTIFIER_CSR(0x0C)
-#define CSR_IDENTIFIER_FREQ3 IDENTIFIER_CSR(0x10)
-#define CSR_IDENTIFIER_FREQ2 IDENTIFIER_CSR(0x14)
-#define CSR_IDENTIFIER_FREQ1 IDENTIFIER_CSR(0x18)
-#define CSR_IDENTIFIER_FREQ0 IDENTIFIER_CSR(0x1C)
-
-#endif /* __HW_IDENTIFIER_H */
#define SDRAM_BASE 0x40000000
+#define MINIMAC_RX0_BASE 0xb0000000
+#define MINIMAC_RX1_BASE 0xb0000800
+#define MINIMAC_TX_BASE 0xb0001000
+
#endif /* __HW_MEM_H */
+++ /dev/null
-#ifndef __HW_MINIMAC_H
-#define __HW_MINIMAC_H
-
-#include <hw/common.h>
-#include <csrbase.h>
-
-#define MINIMAC_CSR(x) MMPTR(MINIMAC_BASE+(x))
-
-#define CSR_MINIMAC_PHYRST MINIMAC_CSR(0x00)
-
-#define CSR_MINIMAC_RXCOUNT0H MINIMAC_CSR(0x04)
-#define CSR_MINIMAC_RXCOUNT0L MINIMAC_CSR(0x08)
-#define CSR_MINIMAC_RXCOUNT1H MINIMAC_CSR(0x0C)
-#define CSR_MINIMAC_RXCOUNT1L MINIMAC_CSR(0x10)
-
-#define CSR_MINIMAC_TXCOUNTH MINIMAC_CSR(0x14)
-#define CSR_MINIMAC_TXCOUNTL MINIMAC_CSR(0x18)
-#define CSR_MINIMAC_TXSTART MINIMAC_CSR(0x1C)
-
-#define CSR_MINIMAC_EV_STAT MINIMAC_CSR(0x20)
-#define CSR_MINIMAC_EV_PENDING MINIMAC_CSR(0x24)
-#define CSR_MINIMAC_EV_ENABLE MINIMAC_CSR(0x28)
-
-#define MINIMAC_EV_RX0 0x1
-#define MINIMAC_EV_RX1 0x2
-#define MINIMAC_EV_TX 0x4
-
-#define MINIMAC_RX0_BASE 0xb0000000
-#define MINIMAC_RX1_BASE 0xb0000800
-#define MINIMAC_TX_BASE 0xb0001000
-
-#endif /* __HW_MINIMAC_H */
+++ /dev/null
-#ifndef __HW_TIMER_H
-#define __HW_TIMER_H
-
-#include <hw/common.h>
-#include <csrbase.h>
-
-#define TIMER0_CSR(x) MMPTR(TIMER0_BASE+(x))
-
-#define CSR_TIMER0_EN TIMER0_CSR(0x00)
-
-#define CSR_TIMER0_COUNT3 TIMER0_CSR(0x04)
-#define CSR_TIMER0_COUNT2 TIMER0_CSR(0x08)
-#define CSR_TIMER0_COUNT1 TIMER0_CSR(0x0C)
-#define CSR_TIMER0_COUNT0 TIMER0_CSR(0x10)
-
-#define CSR_TIMER0_RELOAD3 TIMER0_CSR(0x14)
-#define CSR_TIMER0_RELOAD2 TIMER0_CSR(0x18)
-#define CSR_TIMER0_RELOAD1 TIMER0_CSR(0x1C)
-#define CSR_TIMER0_RELOAD0 TIMER0_CSR(0x20)
-
-#define CSR_TIMER0_EV_STAT TIMER0_CSR(0x24)
-#define CSR_TIMER0_EV_PENDING TIMER0_CSR(0x28)
-#define CSR_TIMER0_EV_ENABLE TIMER0_CSR(0x2C)
-
-#define TIMER0_EV 0x1
-
-#endif /* __HW_TIMER_H */
+++ /dev/null
-#ifndef __HW_UART_H
-#define __HW_UART_H
-
-#include <hw/common.h>
-#include <csrbase.h>
-
-#define UART_CSR(x) MMPTR(UART_BASE+(x))
-
-#define CSR_UART_RXTX UART_CSR(0x00)
-#define CSR_UART_DIVISORH UART_CSR(0x04)
-#define CSR_UART_DIVISORL UART_CSR(0x08)
-
-#define CSR_UART_EV_STAT UART_CSR(0x0c)
-#define CSR_UART_EV_PENDING UART_CSR(0x10)
-#define CSR_UART_EV_ENABLE UART_CSR(0x14)
-
-#define UART_EV_TX 0x1
-#define UART_EV_RX 0x2
-
-#endif /* __HW_UART_H */
-#include <hw/identifier.h>
-#include <hw/gpio.h>
+#include <hw/csr.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
static const struct board_desc *get_board_desc(void)
{
- return get_board_desc_id((CSR_IDENTIFIER_SYSTEMH << 8) | CSR_IDENTIFIER_SYSTEML);
+ return get_board_desc_id(identifier_sysid_read());
}
int get_pcb_revision(void)
{
unsigned int id;
- id = CSR_IDENTIFIER_VERSIONH;
- *major = (id & 0xf0) >> 4;
- *minor = id & 0x0f;
- id = CSR_IDENTIFIER_VERSIONL;
- *subminor = (id & 0xf0) >> 4;
- *rc = id & 0x0f;
+ id = identifier_version_read();
+ *major = (id & 0xf000) >> 12;
+ *minor = (id & 0x0f00) >> 8;
+ *subminor = (id & 0x00f0) >> 4;
+ *rc = id & 0x000f;
}
void get_soc_version_formatted(char *version)
-#include <hw/timer.h>
-#include <hw/identifier.h>
+#include <hw/csr.h>
#include "timer.h"
unsigned int get_system_frequency(void)
{
- return (CSR_IDENTIFIER_FREQ3 << 24)
- |(CSR_IDENTIFIER_FREQ2 << 16)
- |(CSR_IDENTIFIER_FREQ1 << 8)
- |CSR_IDENTIFIER_FREQ0;
+ return identifier_frequency_read();
}
void timer_enable(int en)
{
- CSR_TIMER0_EN = en;
+ timer0_en_write(en);
}
unsigned int timer_get(void)
{
- return (CSR_TIMER0_COUNT3 << 24)
- |(CSR_TIMER0_COUNT2 << 16)
- |(CSR_TIMER0_COUNT1 << 8)
- |CSR_TIMER0_COUNT0;
+ return timer0_value_read();
}
void timer_set_counter(unsigned int value)
{
- CSR_TIMER0_COUNT3 = (value & 0xff000000) >> 24;
- CSR_TIMER0_COUNT2 = (value & 0x00ff0000) >> 16;
- CSR_TIMER0_COUNT1 = (value & 0x0000ff00) >> 8;
- CSR_TIMER0_COUNT0 = value & 0x000000ff;
+ timer0_value_write(value);
}
void timer_set_reload(unsigned int value)
{
- CSR_TIMER0_RELOAD3 = (value & 0xff000000) >> 24;
- CSR_TIMER0_RELOAD2 = (value & 0x00ff0000) >> 16;
- CSR_TIMER0_RELOAD1 = (value & 0x0000ff00) >> 8;
- CSR_TIMER0_RELOAD0 = value & 0x000000ff;
+ timer0_reload_write(value);
}
void busy_wait(unsigned int ds)
#include <uart.h>
#include <irq.h>
-#include <hw/uart.h>
-#include <interrupt.h>
+#include <hw/csr.h>
+#include <hw/flags.h>
/*
* Buffer sizes must be a power of 2 so that modulos can be computed
{
unsigned int stat;
- stat = CSR_UART_EV_PENDING;
+ stat = uart_ev_pending_read();
if(stat & UART_EV_RX) {
- rx_buf[rx_produce] = CSR_UART_RXTX;
+ rx_buf[rx_produce] = uart_rxtx_read();
rx_produce = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX;
}
if(stat & UART_EV_TX) {
if(tx_level > 0) {
- CSR_UART_RXTX = tx_buf[tx_consume];
+ uart_rxtx_write(tx_buf[tx_consume]);
tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
tx_level--;
} else
tx_cts = 1;
}
- CSR_UART_EV_PENDING = stat;
+ uart_ev_pending_write(stat);
}
/* Do not use in interrupt handlers! */
if(tx_cts) {
tx_cts = 0;
- CSR_UART_RXTX = c;
+ uart_rxtx_write(c);
} else {
tx_buf[tx_produce] = c;
tx_produce = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
tx_cts = 1;
tx_level = 0;
- /* ack any events */
- CSR_UART_EV_PENDING = CSR_UART_EV_PENDING;
-
- /* enable interrupts */
- CSR_UART_EV_ENABLE = UART_EV_TX | UART_EV_RX;
-
+ uart_ev_pending_write(uart_ev_pending_read());
+ uart_ev_enable_write(UART_EV_TX | UART_EV_RX);
mask = irq_getmask();
mask |= 1 << UART_INTERRUPT;
irq_setmask(mask);
from fractions import Fraction
from math import ceil
+from operator import itemgetter
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
-from cmacros import get_macros
+from cif import get_macros
MHz = 1000000
clk_freq = (83 + Fraction(1, 3))*MHz
write_time=16
)
-csr_macros = get_macros("common/csrbase.h")
-def csr_offset(name):
- base = int(csr_macros[name + "_BASE"], 0)
- assert((base >= 0xe0000000) and (base <= 0xe0010000))
- return (base - 0xe0000000)//0x800
-
-interrupt_macros = get_macros("common/interrupt.h")
-def interrupt_n(name):
- return int(interrupt_macros[name + "_INTERRUPT"], 0)
-
version = get_macros("common/version.h")["VERSION"][1:-1]
-def csr_address_map(name, memory):
- if memory is not None:
- name += "_" + memory.name_override
- return csr_offset(name.upper())
-
class SoC(Module):
+ csr_base = 0xe0000000
+ csr_map = {
+ "uart": 0,
+ "dfii": 1,
+ "identifier": 2,
+ "timer0": 3,
+ "minimac": 4,
+ "fb": 5,
+ "asmiprobe": 6,
+ "dvisampler0": 7,
+ "dvisampler0_edid_mem": 8,
+ "dvisampler1": 9,
+ "dvisampler1_edid_mem": 10,
+ }
+
+ interrupt_map = {
+ "uart": 0,
+ "timer0": 1,
+ "minimac": 2,
+ }
+
def __init__(self):
#
# ASMI
self.submodules.dvisampler0 = dvisampler.DVISampler("02")
self.submodules.dvisampler1 = dvisampler.DVISampler("02")
- self.submodules.csrbankarray = csrgen.BankArray(self, csr_address_map)
+ self.submodules.csrbankarray = csrgen.BankArray(self,
+ lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
#
# Interrupts
#
- self.comb += [
- self.cpu.interrupt[interrupt_n("UART")].eq(self.uart.ev.irq),
- self.cpu.interrupt[interrupt_n("TIMER0")].eq(self.timer0.ev.irq),
- self.cpu.interrupt[interrupt_n("MINIMAC")].eq(self.minimac.ev.irq)
- ]
+ for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
+ self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
#
# Clocking
projects / litex.git / commitdiff