class SVP64ALUTestCase(TestAccumulatorBase):
def case_1_sv_add(self):
- """lst = ['sv.add 1.v, 5.v, 9.v']
+ """>>> lst = ['sv.add 1.v, 5.v, 9.v']
adds:
1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
initial_svstate=svstate)
def case_2_sv_add_scalar(self):
- """lst = ['sv.add 1, 5, 9']
+ """>>> lst = ['sv.add 1, 5, 9']
adds:
1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
"""
initial_svstate=svstate)
def case_3_sv_check_extra(self):
- """lst = ['sv.add 13.v, 10.v, 7.v']
+ """>>> lst = ['sv.add 13.v, 10.v, 7.v']
adds:
13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012
initial_svstate=svstate)
def case_4_sv_add_(self):
- """lst = ['sv.add. 1.v, 5.v, 9.v']
+ """>>> lst = ['sv.add. 1.v, 5.v, 9.v']
adds when Rc=1: TODO CRs higher up
1 = 5 + 9 => 0 = -1+1 CR0=0b100
2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
initial_svstate=svstate)
def case_5_sv_check_vl_0(self):
- """lst = [
+ """>>> lst = [
'sv.add 13.v, 10.v, 7.v', # skipped, because VL == 0
'add 1, 5, 9'
]
# checks that SRCSTEP was reset properly after an SV instruction
def case_6_sv_add_multiple(self):
- """lst = [
+ """>>> lst = [
'sv.add 1.v, 5.v, 9.v',
'sv.add 13.v, 10.v, 7.v'
]
initial_svstate=svstate)
def case_7_sv_add_2(self):
- """lst = ['sv.add 1, 5.v, 9.v']
+ """>>> lst = ['sv.add 1, 5.v, 9.v']
adds:
1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
"""
initial_svstate=svstate)
def case_8_sv_add_3(self):
- """lst = ['sv.add 1.v, 5, 9.v']
+ """>>> lst = ['sv.add 1.v, 5, 9.v']
+
adds:
1 = 5 + 9 => 0x5555 = 0x4321+0x1234
2 = 5 + 10 => 0x5432 = 0x4321+0x1111
initial_svstate=svstate)
def case_13_sv_predicated_add(self):
- """lst = [
+ """>>> lst = [
'sv.add/m=r30 1.v, 5.v, 9.v',
'sv.add/m=~r30 13.v, 10.v, 7.v'
]
initial_svstate=svstate)
def case_14_intpred_all_zeros_all_ones(self):
- """lst = [
+ """>>> lst = [
'sv.add/m=r30 1.v, 5.v, 9.v',
'sv.add/m=~r30 13.v, 10.v, 7.v'
]
initial_svstate=svstate)
def case_18_sv_add_cr_pred(self):
- """lst = ['sv.add/m=ne 1.v, 5.v, 9.v']
+ """>>> lst = ['sv.add/m=ne 1.v, 5.v, 9.v']
adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
1 = 5 + 9 => not to be touched (skipped)
class SVP64LogicalTestCase(TestAccumulatorBase):
def case_9_sv_extsw_intpred(self):
- """lst = ['sv.extsb/sm=~r3/dm=r3 5.v, 9.v']
+ """>>> lst = ['sv.extsb/sm=~r3/dm=r3 5.v, 9.v']
extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
works as follows, where any zeros indicate "skip element"
initial_svstate=svstate)
def case_10_intpred_vcompress(self):
- """lst = ['sv.extsb/sm=r3 5.v, 9.v']
+ """>>> lst = ['sv.extsb/sm=r3 5.v, 9.v']
reg num 0 1 2 3 4 5 6 7 8 9 10 11
predicate src r3=0b101 Y N Y
initial_svstate=svstate)
def case_11_intpred_vexpand(self):
- """lst = ['sv.extsb/dm=r3 5.v, 9.v']
+ """>>> lst = ['sv.extsb/dm=r3 5.v, 9.v']
reg num 0 1 2 3 4 5 6 7 8 9 10 11
predicate src always Y Y Y
initial_svstate=svstate)
def case_12_sv_twinpred(self):
- """lst = ['sv.extsb/sm=r3/dm=~r3 5.v, 9.v']
+ """>>> lst = ['sv.extsb/sm=r3/dm=~r3 5.v, 9.v']
reg num 0 1 2 3 4 5 6 7 8 9 10 11
predicate src r3=0b101 Y N Y
initial_svstate=svstate)
def case_15_intpred_reentrant(self):
- """lst = ['sv.extsb/sm=r3/dm=~r3 5.v, 9.v']
+ """>>> lst = ['sv.extsb/sm=r3/dm=~r3 5.v, 9.v']
checks that we are able to resume in the middle of a VL loop,
after an interrupt, or after the user has updated src/dst step
initial_svstate=svstate)
def case_16_shift_one_by_r3_dest(self):
- """lst = ['sv.extsb/dm=1<<r3/sm=r30 5.v, 9.v']
+ """>>> lst = ['sv.extsb/dm=1<<r3/sm=r30 5.v, 9.v']
one option for predicate masks is a single-bit set: 1<<r3.
lots of opportunity for hardware optimisation, it effectively
initial_svstate=svstate)
def case_17_shift_one_by_r3_source(self):
- """lst = ['sv.extsb/sm=1<<r3/dm=r30 5.v, 9.v']
+ """>>> lst = ['sv.extsb/sm=1<<r3/dm=r30 5.v, 9.v']
reg num 0 1 2 3 4 5 6 7 8 9 10 11
src r3=2: 1<<r3=0b100 N N Y
initial_svstate=svstate)
def case_19_crpred_reentrant(self):
- """lst = ['sv.extsb/sm=eq/dm=lt 5.v, 9.v']
+ """>>> lst = ['sv.extsb/sm=eq/dm=lt 5.v, 9.v']
checks reentrant CR predication. note that the source CR-mask
and destination CR-mask use *different bits* of the CR fields,