RISC-V: Make XVentanaCondOps RV64 only

Although XVentanaCondOps instructions are XLEN-agonistic, Ventana's manual
only defines them only for RV64 (because all Ventana's processors implement
RV64).

This commit limits XVentanaCondOps instructions RV64-only to match the
behavior of the manual and LLVM.

Note that this commit alone will not make XVentanaCondOps extension with
RV32 invalid (it just makes XVentanaCondOps on RV32 empty).

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Restrict "vt.maskc" and "vt.maskcn"
	to XLEN=64.

gas/ChangeLog:

	* testsuite/gas/riscv/x-ventana-condops-32.d: New failure test.
	* testsuite/gas/riscv/x-ventana-condops-32.l: Likewise.

diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.d b/gas/testsuite/gas/riscv/x-ventana-condops-32.d
new file mode 100644 (file)
index 0000000..ea67515
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xventanacondops
+#source: x-ventana-condops.s
+#error_output: x-ventana-condops-32.l

diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.l b/gas/testsuite/gas/riscv/x-ventana-condops-32.l
new file mode 100644 (file)
index 0000000..e434caf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.l
@@ -0,0 +1,3 @@
+.*Assembler messages:
+.*Error: unrecognized opcode `vt.maskc a0,a1,a2'
+.*Error: unrecognized opcode `vt.maskcn a0,a3,a4'

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 067e9fdb611fbc6d83c6da6fc59ccd5a6cc093aa..f5416605dcc3756421ba5699cc2789489c756efa 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2174,8 +2174,8 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.sync.s",        0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_S,        MASK_TH_SYNC_S,        match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
-{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
-{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
+{"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
+{"vt.maskcn",  64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
 
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}