targets/genesys2: update self.register_sdram

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 0a7e95a4f8c4a1ad2fff5f2405571345c41cd451..7bb495dcb58a51a64fb9ab50a08ac2720f0196e9 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -61,7 +61,9 @@ class BaseSoC(SoCSDRAM):
                 sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             sdram_module = MT41J256M16(self.clk_freq, "1:4")
-            self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
+            self.register_sdram(self.ddrphy,
+                geom_settings       = sdram_module.geom_settings,
+                timing_settings     = sdram_module.timing_settings)
 
 # EthernetSoC --------------------------------------------------------------------------------------