Fix handling of signed memories

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 40cbbc2a3e9224ab23d4809fce246a42c685dbe8..d9f0039af4d7d8df8ab036ac618b6d46127f48a2 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1300,6 +1300,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
                        cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
 
+                       if (!sign_hint)
+                               is_signed = false;
+
                        return RTLIL::SigSpec(wire);
                }