Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff

diff --cc techlibs/xilinx/abc9_map.v
Simple merge

diff --cc tests/simple_abc9/abc9.v
index 58596d701b2a59c691be31710ecb5bebf1c32357,1844bac20cd313b2e9bfa4f61376e14656f74c5b..65eb01338734f3715e0fe5bfa163c319047a442e
--- 1/tests/simple_abc9/abc9.v
--- 2/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@@ -268,14 -268,7 +268,19 @@@ assign o = { 1'b1, 1'bx }
  assign p = { 1'b1, 1'bx, 1'b0 };
  endmodule
  
- module abc9_test029(input clk, d, r, output reg q);
+ module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
+ always @(posedge clk1) q1 <= d;
+ always @(negedge clk2) q2 <= q1;
+ endmodule
++
++module abc9_test030(input clk, d, r, output reg q);
 +always @(posedge clk or posedge r)
 +    if (r) q <= 1'b0;
 +    else q <= d;
 +endmodule
 +
- module abc9_test030(input clk, d, r, output reg q);
++module abc9_test031(input clk, d, r, output reg q);
 +always @(negedge clk or posedge r)
 +    if (r) q <= 1'b1;
 +    else q <= d;
 +endmodule

diff --cc tests/various/abc9.v
index e53dcdb21d4581bcc95b8658d1230c3981911783,30ebd4e26c9fb410c5f6bcd9c235fab64efa17dd..85828bf30779e9f1ea99449c5bb02ea159ffe3d9
--- 1/tests/various/abc9.v
--- 2/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@@ -9,10 -9,3 +9,10 @@@ wire w
  unknown u(~i, w);
  unknown2 u2(w, o);
  endmodule
- module abc9_test031(input clk, d, r, output reg q);
 +
++module abc9_test032(input clk, d, r, output reg q);
 +initial q = 1'b0;
 +always @(negedge clk or negedge r)
 +    if (r) q <= 1'b0;
 +    else q <= d;
 +endmodule

diff --cc tests/various/abc9.ys
index f7a3f1fa0c9c500814f6258fc5f5611284e2c763,5c9a4075d0d79d40491282a1a23d964127c25a8e..81d0afd1ba0461917576799686e5df4150242d21
--- 1/tests/various/abc9.ys
--- 2/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@@ -22,19 -22,3 +22,19 @@@ abc9 -lut 
  select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
  select -assert-count 1 t:unknown
  select -assert-none t:$lut t:unknown %% t: %D
- hierarchy -top abc9_test031
 +
 +design -load read
++hierarchy -top abc9_test032
 +proc
 +clk2fflogic
 +design -save gold
 +
 +abc9 -lut 4
 +check
 +design -stash gate
 +
 +design -import gold -as gold
 +design -import gate -as gate
 +
 +miter -equiv -flatten -make_assert -make_outputs gold gate miter
 +sat -seq 10 -verify -prove-asserts -show-ports miter