cpu/vexriscv_smp: move litedram import, remove os.path import.

diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index c775ffa223750d656ea63f0fa7d201975662f816..c88c84a4868804a7965340e67d4098dd5791e8d0 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -12,10 +12,7 @@ from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
-from litedram.common import LiteDRAMNativePort
-
 import os
-import os.path
 
 
 CPU_VARIANTS = {
@@ -228,6 +225,7 @@ class VexRiscvSMP(CPU):
                 )
             ]
 
+        from litedram.common import LiteDRAMNativePort
         if "mp" in variant:
             ncpus = int(variant[-2]) # FIXME
             for n in range(ncpus):