add average-add DRAFT pseudocode and CSV

https://bugs.libre-soc.org/show_bug.cgi?id=863

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 7f10262acd30e0afc1aa3d7e64809edfa670a28e..2dc0838d84f5949912fad0ffe33b1a8ce4a34b59 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -1,6 +1,8 @@
 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
+<!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
+<!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
 
-# Fixed Point Signed Max
+# DRAFT Fixed Point Signed Max
 
 X-Form
 
@@ -16,7 +18,7 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
-# Fixed Point Unsighed Max
+# DRAFT Fixed Point Unsigned Max
 
 X-Form
 
@@ -32,7 +34,7 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
-# Fixed Point Signed Min
+# DRAFT Fixed Point Signed Min
 
 X-Form
 
@@ -48,7 +50,7 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
-# Fixed Point Unsighed Min
+# DRAFT Fixed Point Unsigned Min
 
 X-Form
 
@@ -64,3 +66,23 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
+# DRAFT Average Add
+
+X-Form
+
+* avgadd RT,RA,RB (Rc=0)
+* avgadd.  RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    a <- [0] * (XLEN+1)
+    b <- [0] * (XLEN+1)
+    a[1:XLEN] <- (RA)
+    b[1:XLEN] <- (RB)
+    r <- (a + b + 1)
+    RT <- r[0:XLEN-1]
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 4c4834f89290c29c8eda2118c8b27b4b9a45f13c..28d736b97f0df0b7c8d8208c5effcd0aef205f81 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -7,3 +7,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0011001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,maxu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 0101001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c8a60c4e421f35a46145c3a73db99827b23d2cba..2bad589f1f60f255a213eb62c2a6f41796d516f2 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1274,6 +1274,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = asmop
 
+        # and anything avgadd
+        if asmop.startswith('avgadd'):
+            illegal = False
+            ins_name = asmop
+
         # and anything ternlog
         if asmop.startswith('ternlog'):
             illegal = False

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index a54cc270f1ead8399818454b680ffa1660548e27..90a861dafc38d3ca46d4af149c7c524425e0f0d4 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -259,7 +259,8 @@ _insns = [
     "addme", "addmeo", "addo", "addze", "addzeo",
     "addg6s",
     "and", "andc", "andi.", "andis.",
-    "attn",
+    "attn",                                 # AV bitmanip
+    "avgadd",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
     "cbcdtd",
@@ -444,6 +445,7 @@ class MicrOp(Enum):
     OP_FETCH_FAILED = 87
     OP_GREV = 88
     OP_MINMAX = 89
+    OP_AVGADD = 90
 
 
 @unique

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 2c10a23ff347330a4ff4a90c1a563ba092d585e7..675d26b5e21e0d6f279cfd19bdd93057c0d3ae5d 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -441,6 +441,23 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
+        # and avgadd
+        # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
+        if opcode in ['avgadd', ]:
+            if opcode[:6] == 'avgadd':
+                XO = 0b1101001110
+            fields = list(map(int, fields))
+            insn = 22 << (31-5)  # opcode 22, bits 0-5
+            insn |= fields[0] << (31-10)  # RT       , bits 6-10
+            insn |= fields[1] << (31-15)  # RA       , bits 11-15
+            insn |= fields[2] << (31-20)  # RB       , bits 16-20
+            insn |= XO        << (31-30)  # XO       , bits 21..30
+            if opcode.endswith('.'):
+                insn |= 1 << (31-31)     # Rc=1     , bit 31
+            log("maxs", bin(insn))
+            yield ".long 0x%x" % insn
+            return
+
         # identify if is a svp64 mnemonic
         if not opcode.startswith('sv.'):
             yield insn  # unaltered
@@ -1314,6 +1331,7 @@ if __name__ == '__main__':
     lst = [
         'maxs 3,12,5',
         'maxs. 3,12,5',
+        'avgadd 3,12,5',
     ]
     isa = SVP64Asm(lst, macros=macros)
     log("list", list(isa))

diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index 913c5c433a6cda7ba98b5a35e51cada295ac2b5e..5fabe7651379dafc2a17857e1db78fa385ff5882 100644 (file)
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -169,3 +169,55 @@ class AVTestCase(TestAccumulatorBase):
         e.crregs[0] = 0x8 # RT is -ve
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_0_avgadd(self):
+        lst = ["avgadd 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xc523e996a8ff6215
+        initial_regs[2] = 0xe1e5b9cc9864c4a8
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xc523e996a8ff6215
+        e.intregs[2] = 0xe1e5b9cc9864c4a8
+        e.intregs[3] = 0xd384d1b1a0b2135f
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_1_avgadd(self):
+        lst = ["avgadd 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xc523e996a8ff6214
+        initial_regs[2] = 0xe1e5b9cc9864c4a8
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xc523e996a8ff6214
+        e.intregs[2] = 0xe1e5b9cc9864c4a8
+        e.intregs[3] = 0xd384d1b1a0b2135e
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_2_avgadd(self):
+        lst = ["avgadd 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xc523e996a8ff6213
+        initial_regs[2] = 0xe1e5b9cc9864c4a8
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xc523e996a8ff6213
+        e.intregs[2] = 0xe1e5b9cc9864c4a8
+        e.intregs[3] = 0xd384d1b1a0b2135e
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_3_avgadd(self):
+        lst = ["avgadd 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        initial_regs[2] = 0xffffffffffffffff
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xffffffffffffffff
+        e.intregs[2] = 0xffffffffffffffff
+        e.intregs[3] = 0xffffffffffffffff
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+