inorder: se compile fixes

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 8188ac3541245a89b19e71aa9df89c925eb75be0..e8608181f374b107497ada94ae7171eb8d31a151 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -702,7 +702,10 @@ InOrderCPU::tick()
 
     ++numCycles;
 
+#if FULL_SYSTEM
     checkForInterrupts();
+#endif
+
     bool pipes_idle = true;
     //Tick each of the stages
     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 94f2d046138f8a7c00db6971eb844b6329036910..350e2d1dd81eb735b99937d8fe78aafddc6b49be 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -454,8 +454,8 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
         // schedule a time to process the tlb miss.
         // latency hardcoded to 1 (for now), but will be updated
         // when timing translation gets added in
-        scheduleEvent(slot_idx, 1);
         unsigned slot_idx = cache_req->getSlot();
+        scheduleEvent(slot_idx, 1);
 #endif
 
         // Mark it as complete so it can pass through next stage.