freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs

The first pre_assign_inputs loop doesn't pre-assign sysvals, so skip the
second part for sysvals.

The sysvals don't need to be pre-assigned since the state for those isn't
shared between binning / nonbinning shaders.

Fixes assert failures in cases where the sysvals didn't end up in the same
registers for binning / nonbinning.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 82149c98e60160f17abd4cdccb2df1af44f4fd96..b6fc39f2fb173ef94864f2807019f419107ff89b 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3495,7 +3495,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
                assert(in->opc == OPC_META_INPUT);
                unsigned inidx = in->input.inidx;
 
-               if (pre_assign_inputs) {
+               if (pre_assign_inputs && !so->inputs[inidx].sysval) {
                        if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
                                compile_assert(ctx, in->regs[0]->num ==
                                                so->nonbinning->inputs[inidx].regid);