testsuite: adjustments for amdgcn

2020-03-25  Andrew Stubbs  <ams@codesourcery.com>

	gcc/testsuite/
	* gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn.
	* lib/target-supports.exp (check_effective_target_vect_unpack):
	Add amdgcn.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fe8460c76647eafd094f77a19346ed61ad70d8a4..e750dcbc7900157e7524034bf851797c5bc2942f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-25  Andrew Stubbs  <ams@codesourcery.com>
+
+       * gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn.
+       * lib/target-supports.exp (check_effective_target_vect_unpack):
+       Add amdgcn.
+
 2020-03-25  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/94292

diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index 813b1af089a81e941663a7219f95d3d5a61c236b..fe52d18525a339ce8d7814974bbd5a925762d871 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -19,5 +19,6 @@ void foo(unsigned *p1, unsigned short *p2)
 
 /* Disable for SVE because for long or variable-length vectors we don't
    get an unrolled epilogue loop.  Also disable for AArch64 Advanced SIMD,
-   because there we can vectorize the epilogue using mixed vector sizes.  */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64*-*-* } } } } */
+   because there we can vectorize the epilogue using mixed vector sizes.
+   Likewise for AMD GCN.  */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 10353af580a875c2bd8303d226ccd1e92bd1bfcb..3654e7bc232e7513a59497d8d58823dc46be926e 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6717,7 +6717,8 @@ proc check_effective_target_vect_unpack { } {
              || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
                 && [check_effective_target_arm_little_endian])
             || ([istarget s390*-*-*]
-                && [check_effective_target_s390_vx]) }}]
+                && [check_effective_target_s390_vx])
+            || [istarget amdgcn*-*-*] }}]
 }
 
 # Return 1 if the target plus current options does not guarantee