add quick preamble header

diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py
index 5d311c69a14b59b0e56b68382a1129af2ecfd82c..15281d243b4647e16ca546b3b75cb09c8af76d88 100644 (file)
--- a/src/openpower/cyclemodel/inorder.py
+++ b/src/openpower/cyclemodel/inorder.py
@@ -1,5 +1,9 @@
 #!/usr/bin/env python3
 # An In-order cycle-accurate model of a Power ISA 3.0 hardware implementation
+# LGPLv3+
+# Funded by NLnet
+#
+# Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=1039
 
 class RegisterWrite(set):
     """RegisterWrite: contains the set of Read-after-Write Hazards.