rs6000.md (extendtfif2): Add missing 128-bit conversion insn that shows up when...

2018-06-21  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (extendtfif2): Add missing 128-bit
	conversion insn that shows up when pr85657-3.c is compiled using
	IEEE 128-bit long double.

From-SVN: r261867

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 902f8df8b58e5c5f49051f7ad8f909458e0b75d4..ff854f851e62132013a6f7887dd1784f920b5cc4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-21  Michael Meissner  <meissner@linux.ibm.com>
+
+       * config/rs6000/rs6000.md (extendtfif2): Add missing 128-bit
+       conversion insn that shows up when pr85657-3.c is compiled using
+       IEEE 128-bit long double.
+
 2018-06-21  Eric Botcazou  <ebotcazou@adacore.com>
 
        * cfgrtl.c (fixup_reorder_chain): Do not emit NOPs in DECL_IGNORED_P

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e5c4cf176ea0f8f5e820fc3a5d29e45f77899089..3044e6eb475450baaa7c3eb344500954f8348dc3 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8158,6 +8158,15 @@
   DONE;
 })
 
+(define_expand "extendtfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand")
+       (float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
 (define_expand "trunciftf2"
   [(set (match_operand:TF 0 "gpc_reg_operand")
        (float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]