Do not make ff[MP]mux semioptional, use sigmap

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index a497d0a48286ca2a0fb2223441e360e1218ed8a3..6e82ffac353ba77ce120c5bc6aae38798f42a000 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -121,7 +121,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                                cell->setPort("\\CEM", State::S1);
                        SigSpec D = st.ffM->getPort("\\D");
                        SigSpec Q = st.ffM->getPort("\\Q");
-                       P.replace(/*pm.sigmap*/(D), Q);
+                       P.replace(pm.sigmap(D), Q);
 
                        cell->setParam("\\MREG", State::S1);
                        pm.autoremove(st.ffM);
@@ -135,7 +135,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                                cell->setPort("\\CEP", State::S1);
                        SigSpec D = st.ffP->getPort("\\D");
                        SigSpec Q = st.ffP->getPort("\\Q");
-                       P.replace(/*pm.sigmap*/(D), Q);
+                       P.replace(pm.sigmap(D), Q);
                        st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
 
                        cell->setParam("\\PREG", State::S1);
@@ -149,6 +149,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                if (st.ffB)
                        log(" ffB:%s", log_id(st.ffB));
 
+               if (st.ffM)
+                       log(" ffM:%s", log_id(st.ffM));
+
                if (st.ffP)
                        log(" ffP:%s", log_id(st.ffP));
 

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index a2a6f2ef0a00cbb7ebdceb467f1174c1909ebf59..d7632da6fedfaeae0599c2f9eca416b0f908d2e1 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -120,7 +120,7 @@ match ffMmux
        filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
        filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
        set ffMmuxAB AB
-       semioptional
+       optional
 endmatch
 
 code sigM
@@ -207,12 +207,12 @@ match ffPmux
        filter port(ffPmux, AB) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
        filter nusers(sigP.extract_end(GetSize(port(ffPmux, AB)))) <= 1
        set ffPmuxAB AB
-       semioptional
+       optional
 endmatch
 
 code sigP
        if (ffPmux)
-               sigP = port(ffPmux, \Y);
+               sigP.replace(port(ffPmux, ffPmuxAB), port(ffPmux, \Y));
 endcode
 
 match ffP
@@ -243,6 +243,9 @@ code ffP sigP clock
 
                sigP.replace(port(ffP, \D), port(ffP, \Q));
        }
+       // Cannot have ffPmux enable mux without ffP
+       else if (ffPmux)
+               reject;
 endcode
 
 match postAddMux