soc/cores/clock: remove return on S7PLL.create_clkout

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index ed8e68c11e9f1850e7149b6e878529e14c6d1400..aeb1445400e10d4f965650d6fd6cceb4d034912a 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -60,8 +60,6 @@ class S7Clocking(Module, AutoCSR):
             else:
                 raise ValueError
 
-        return clkout_buf
-
     def compute_config(self):
         config = {}
         config["divclk_divide"] = 1