;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"
(const (symbol_ref "rs6000_cpu_attr")))
; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
(define_function_unit "iu" 1 0
(and (eq_attr "type" "load")
- (eq_attr "cpu" "rios1,ppc403,ppc601"))
+ (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
2 1)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "store,fpstore")
- (eq_attr "cpu" "rios1,ppc403,ppc601"))
+ (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
1 1)
(define_function_unit "fpu" 1 0
; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "integer")
- (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
+ (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
1 1)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "cr_logical")
- (eq_attr "cpu" "mpccore,ppc403,ppc601"))
+ (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601"))
1 1)
(define_function_unit "iu" 1 0
4 4)
(define_function_unit "iu" 1 0
- (and (eq_attr "type" "imul,imul2,imul3")
- (eq_attr "cpu" "rios1,ppc601,ppc603"))
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "ppc405"))
+ 4 3)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul2,imul3")
+ (eq_attr "cpu" "ppc405"))
+ 3 2)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul")
+ (eq_attr "cpu" "rios1"))
5 5)
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul2")
+ (eq_attr "cpu" "rios1"))
+ 4 4)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul3")
+ (eq_attr "cpu" "rios1"))
+ 3 3)
+
(define_function_unit "iu" 1 0
(and (eq_attr "type" "imul,imul2,imul3")
+ (eq_attr "cpu" "ppc601,ppc603"))
+ 5 5)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul")
(eq_attr "cpu" "rs64a"))
- 20 14)
+ 20 20)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul2")
+ (eq_attr "cpu" "rs64a"))
+ 12 12)
+
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "imul3")
+ (eq_attr "cpu" "rs64a"))
+ 8 8)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "lmul")
(eq_attr "cpu" "ppc403"))
33 33)
+(define_function_unit "iu" 1 0
+ (and (eq_attr "type" "idiv")
+ (eq_attr "cpu" "ppc405"))
+ 35 35)
+
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc601"))
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imul2,imul3")
+ (eq_attr "cpu" "ppc604e"))
+ 2 1)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc620,ppc630"))
5 3)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "imul2")
(eq_attr "cpu" "ppc620,ppc630"))
- 5 3)
+ 4 3)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imul2,imul3")
- (eq_attr "cpu" "ppc604e"))
- 2 1)
+ (and (eq_attr "type" "imul3")
+ (eq_attr "cpu" "ppc620,ppc630"))
+ 3 3)
+
+(define_function_unit "imuldiv" 1 0
+ (and (eq_attr "type" "lmul")
+ (eq_attr "cpu" "ppc620,ppc630"))
+ 7 5)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
(define_function_unit "iu" 1 0
(and (eq_attr "type" "compare,delayed_compare")
- (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
+ (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
3 1)
; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
(define_function_unit "bpu" 1 0
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
+ (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
4 1)
(define_function_unit "sru" 1 0