Added log_warning() API

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 2aff94198b7d5e3c461eede7ebd400ac19af9083..390822ed3f9fb382d970acb8b1f496f0ac0fc4e1 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -58,7 +58,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 
                if (design->modules_.count(cell->type) == 0)
                {
-                       log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
+                       log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
                                        RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
                        for (auto &conn : cell->connections()) {
                                RTLIL::SigSpec sig = sigmap(conn.second);

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 68c45179d0601b1ca48a311ceb2fd36bd6c73d59..4a102370b7bc314d7b2a0e350882d60df14f384a 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -869,7 +869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        case AST_REALVALUE:
                {
                        RTLIL::SigSpec sig = realAsConst(width_hint);
-                       log("Warning: converting real value %e to binary %s at %s:%d.\n",
+                       log_warning("converting real value %e to binary %s at %s:%d.\n",
                                        realvalue, log_signal(sig), filename.c_str(), linenum);
                        return sig;
                }
@@ -890,7 +890,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
                                wire->name = str;
                                if (flag_autowire)
-                                       log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+                                       log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
                                else
                                        log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
                        }
@@ -955,10 +955,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                                chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
                                        if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
                                                if (chunk.width == 1)
-                                                       log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
+                                                       log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
                                                                        str.c_str(), filename.c_str(), linenum);
                                                else
-                                                       log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
+                                                       log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
                                                                        str.c_str(), filename.c_str(), linenum, chunk.width);
                                                chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
                                        } else {
@@ -972,10 +972,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                                        chunk.offset += add_undef_bits_lsb;
                                                }
                                                if (add_undef_bits_lsb)
-                                                       log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
+                                                       log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
                                                                        str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb);
                                                if (add_undef_bits_msb)
-                                                       log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
+                                                       log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
                                                                        str.c_str(), filename.c_str(), linenum, add_undef_bits_msb);
                                        }
                                }

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index d8fdb4c5efc22e2555bd2b150466a41791e53ac6..a78fafbd13a9f55cda8b12b69d75e430d02ba1f9 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -102,7 +102,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
                        verbose_activate:
                                if (mem2reg_set.count(mem) == 0) {
-                                       log("Warning: Replacing memory %s with list of registers.", mem->str.c_str());
+                                       log_warning("Replacing memory %s with list of registers.", mem->str.c_str());
                                        bool first_element = true;
                                        for (auto &place : mem2reg_places[it.first]) {
                                                log("%s%s", first_element ? " See " : ", ", place.c_str());
@@ -648,7 +648,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
                        int width = children[1]->range_left - children[1]->range_right + 1;
                        if (children[0]->type == AST_REALVALUE) {
                                RTLIL::Const constvalue = children[0]->realAsConst(width);
-                               log("Warning: converting real value %e to binary %s at %s:%d.\n",
+                               log_warning("converting real value %e to binary %s at %s:%d.\n",
                                                children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum);
                                delete children[0];
                                children[0] = mkconst_bits(constvalue.bits, sign_hint);
@@ -690,7 +690,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
                        }
                }
                if (current_scope.count(str) == 0) {
-                       // log("Warning: Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str());
+                       // log_warning("Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str());
                        AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
                        auto_wire->str = str;
                        current_ast_mod->children.push_back(auto_wire);
@@ -1260,7 +1260,7 @@ skip_dynamic_range_lvalue_expansion:;
                std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
 
                if (type == AST_ASSIGN_EQ)
-                       log("Warning: Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
+                       log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
                                        filename.c_str(), linenum);
 
                int mem_width, mem_size, addr_bits;

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 44dfba0a80e20ecc80cb5f77e45d5b17ec54f407..79abcf245536b635ead89dc9ed902b0f8ff660b1 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -730,7 +730,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
                        if (import_netlist_instance_cells(module, net_map, inst))
                                continue;
                        if (inst->IsOperator())
-                               log("Warning: Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
+                               log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
                } else {
                        if (import_netlist_instance_gates(module, net_map, inst))
                                continue;

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index ae16ebf78021ea34e203ec34c840001ca9dc7268..5e739842b1302fff9602186bafd4e32cbd8e7367 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -254,8 +254,8 @@ supply1 { return TOK_SUPPLY1; }
 }
 
 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
-       log("Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n");
-       log("It is strongly suggested to use `ifdef constructs instead!\n");
+       log_warning("Found one of those horrible `(synopsys|synthesis) translate_off' comments.\n"
+                       "It is strongly suggested to use `ifdef constructs instead!\n");
        BEGIN(SYNOPSYS_TRANSLATE_OFF);
 }
 <SYNOPSYS_TRANSLATE_OFF>.    /* ignore synopsys translate_off body */
@@ -266,13 +266,13 @@ supply1 { return TOK_SUPPLY1; }
        BEGIN(SYNOPSYS_FLAGS);
 }
 <SYNOPSYS_FLAGS>full_case {
-       log("Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.\n");
-       log("It is strongly suggested to use verilog x-values and default branches instead!\n");
+       log_warning("Found one of those horrible `(synopsys|synthesis) full_case' comments.\n"
+                       "It is strongly suggested to use verilog x-values and default branches instead!\n");
        return TOK_SYNOPSYS_FULL_CASE;
 }
 <SYNOPSYS_FLAGS>parallel_case {
-       log("Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n");
-       log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
+       log_warning("Found one of those horrible `(synopsys|synthesis) parallel_case' comments.\n"
+                       "It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
        return TOK_SYNOPSYS_PARALLEL_CASE;
 }
 <SYNOPSYS_FLAGS>. /* ignore everything else */

diff --git a/kernel/cost.h b/kernel/cost.h
index 5e99df993fafe2b571d00c224a5178c220274c3e..61a693b9c74718fe0daf048326843e13dc297187 100644 (file)
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -70,7 +70,7 @@ int get_cell_cost(RTLIL::IdString type, const std::map<RTLIL::IdString, RTLIL::C
                return module_cost;
        }
 
-       log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
+       log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
        return 1;
 }
 

diff --git a/kernel/log.cc b/kernel/log.cc
index 9f5f03b2f15ea0507b6a75133e084f3c5dee7db5..9f9c4db9f5fae125f9480f963dc412c8679ea84f 100644 (file)
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -152,6 +152,19 @@ void logv_header(const char *format, va_list ap)
                log_files.pop_back();
 }
 
+void logv_warning(const char *format, va_list ap)
+{
+       if (log_errfile != NULL)
+               log_files.push_back(log_errfile);
+
+       log("Warning: ");
+       logv(format, ap);
+       log_flush();
+
+       if (log_errfile != NULL)
+               log_files.pop_back();
+}
+
 void logv_error(const char *format, va_list ap)
 {
        if (log_errfile != NULL)
@@ -179,6 +192,14 @@ void log_header(const char *format, ...)
        va_end(ap);
 }
 
+void log_warning(const char *format, ...)
+{
+       va_list ap;
+       va_start(ap, format);
+       logv_warning(format, ap);
+       va_end(ap);
+}
+
 void log_error(const char *format, ...)
 {
        va_list ap;
@@ -304,14 +325,14 @@ std::map<std::string, std::pair<std::string, int>> get_coverage_data()
 
        for (auto &it : extra_coverage_data) {
                if (coverage_data.count(it.first))
-                       log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str());
+                       log_warning("found duplicate coverage id \"%s\".\n", it.first.c_str());
                coverage_data[it.first].first = it.second.first;
                coverage_data[it.first].second += it.second.second;
        }
 
        for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
                if (coverage_data.count(p->id))
-                       log("WARNING: found duplicate coverage id \"%s\".\n", p->id);
+                       log_warning("found duplicate coverage id \"%s\".\n", p->id);
                coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
                coverage_data[p->id].second += p->counter;
        }

diff --git a/kernel/log.h b/kernel/log.h
index 93e8144a0905a1d3d7a4302a1581ffefb9503a39..b003aba22c64f7b0a9e629e4837d0d059f56a4ee 100644 (file)
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -51,10 +51,12 @@ extern int log_verbose_level;
 
 void logv(const char *format, va_list ap);
 void logv_header(const char *format, va_list ap);
+void logv_warning(const char *format, va_list ap);
+_NORETURN_ void logv_error(const char *format, va_list ap) __attribute__((noreturn));
 
-void logv_error(const char *format, va_list ap) __attribute__((noreturn));
 void log(const char *format, ...)  __attribute__((format(printf, 1, 2)));
 void log_header(const char *format, ...) __attribute__((format(printf, 1, 2)));
+void log_warning(const char *format, ...) __attribute__((format(printf, 1, 2)));
 _NORETURN_ void log_error(const char *format, ...) __attribute__((format(printf, 1, 2))) __attribute__((noreturn));
 _NORETURN_ void log_cmd_error(const char *format, ...) __attribute__((format(printf, 1, 2))) __attribute__((noreturn));
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8cfc0c5f981ef9930b3fe66b3e5ac0d9cdc0d3c0..803d783af919d009eaa408d6a3c4bfcaa5ab968f 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -440,7 +440,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
                if (selected_whole_module(it.first))
                        result.push_back(it.second);
                else if (selected_module(it.first))
-                       log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
+                       log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
        return result;
 }
 
@@ -1062,14 +1062,14 @@ bool RTLIL::Module::has_processes() const
 bool RTLIL::Module::has_memories_warn() const
 {
        if (!memories.empty())
-               log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
+               log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
        return !memories.empty();
 }
 
 bool RTLIL::Module::has_processes_warn() const
 {
        if (!processes.empty())
-               log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
+               log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
        return !processes.empty();
 }
 

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 8e42fe15f073a0856ae8510ddd92d1c199220d27..7f841673f0e586b6e36c7d47bc175d50cd448e84 100644 (file)
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -532,7 +532,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode)
        }
 
        if (rem_objects == 0)
-               log("Warning: reached configured limit at `%s'.\n", arg.c_str());
+               log_warning("reached configured limit at `%s'.\n", arg.c_str());
 }
 
 static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 84932e963a9d8e5ac4ef80b43ec3ce3f408e404b..c89553c6bc30036783701d89da7ee960a3428dc9 100644 (file)
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -43,7 +43,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
                return true;
 
        if (recursion_monitor.check_any(sig)) {
-               log("Warning: logic loop in mux tree at signal %s in module %s.\n",
+               log_warning("logic loop in mux tree at signal %s in module %s.\n",
                                log_signal(sig), RTLIL::id2cstr(module->name));
                return false;
        }

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 68a441f405f5eea6636daef14d1cc735fcc9e221..8d4012c534e03d8d81e34219a81fae0c8e7c7bd7 100644 (file)
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -85,7 +85,7 @@ struct SubmodWorker
                                for (auto &conn : cell->connections())
                                        flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
                        } else {
-                               log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
+                               log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
                                for (auto &conn : cell->connections())
                                        flag_signal(conn.second, true, true, true, false, false);
                        }
@@ -102,7 +102,7 @@ struct SubmodWorker
                                for (auto &conn : cell->connections())
                                        flag_signal(conn.second, false, false, false, true, true);
                                if (flag_found_something)
-                                       log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
+                                       log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
                        }
                }
 

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index b632cdabbb6ea589273eb410026716d0a0838e73..76842da6bc73c7561a0afedbf3217c02fb101139 100644 (file)
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -333,12 +333,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 
                if (many_async_rules.size() > 0)
                {
-                       log("WARNING: Complex async reset for dff `%s'.\n", log_signal(sig));
+                       log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
                        gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
                }
                else if (!rstval.is_fully_const() && !ce.eval(rstval))
                {
-                       log("WARNING: Async reset value `%s' is not constant!\n", log_signal(rstval));
+                       log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
                        gen_dffsr(mod, insig, rstval, sig,
                                        sync_edge->type == RTLIL::SyncType::STp,
                                        sync_level && sync_level->type == RTLIL::SyncType::ST1,

diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 7a5a02a9bb0df4250e3be97d22b808769bdfaca8..62534ec0b258abda8383ca2fea66a58af30125f2 100644 (file)
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -277,7 +277,7 @@ struct VlogHammerReporter
 
                                while (!ce.eval(sig, undef)) {
                                        // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
-                                       log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
+                                       log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
                                        ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
                                }
 

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index d5d1d9160cb101c073ad31bf12942977428c77c8..b73417e87c24761d7f40a78b1f4b493db54761d0 100644 (file)
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -116,7 +116,7 @@ struct SatHelper
                        }
 
                        if (removed_bits.size())
-                               log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
+                               log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits));
 
                        if (lhs.size()) {
                                log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
@@ -327,7 +327,7 @@ struct SatHelper
                                                        show_drivers.insert(sigmap(p.second), c.second);
                                        import_cell_counter++;
                                } else if (ignore_unknown_cells)
-                                       log("Warning: Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
+                                       log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
                                else
                                        log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
                }