remove Layer in module names

diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py
index 2dcc5ab571493b406c10ac179975cc1f39215bf8..47a8f29c4b207c6c0accd47f1f77411a98dafde2 100644 (file)
--- a/lib/sata/link/__init__.py
+++ b/lib/sata/link/__init__.py
@@ -13,7 +13,7 @@ from_rx = [
        ("det", 32)
 ]
 
-class SATALinkLayerTX(Module):
+class SATALinkTX(Module):
        def __init__(self, phy):
                self.sink = Sink(link_layout(32))
                self.from_rx = Sink(from_rx)
@@ -111,7 +111,7 @@ class SATALinkLayerTX(Module):
                        )
                )
 
-class SATALinkLayerRX(Module):
+class SATALinkRX(Module):
        def __init__(self, phy):
                self.source = Source(link_layout(32))
                self.to_tx = Source(from_rx)
@@ -212,9 +212,9 @@ class SATALinkLayerRX(Module):
                        self.to_tx.det.eq(det)
                ]
 
-class SATALinkLayer(Module):
+class SATALink(Module):
        def __init__(self, phy):
-               self.submodules.tx = SATALinkLayerTX(phy)
-               self.submodules.rx = SATALinkLayerRX(phy)
+               self.submodules.tx = SATALinkTX(phy)
+               self.submodules.rx = SATALinkRX(phy)
                self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
                self.sink, self.source = self.tx.sink, self.rx.source

diff --git a/lib/sata/test/link_tb.py b/lib/sata/test/link_tb.py
index 1dded9a44f439fc3c92d4230b8ee01680786d9a8..d56358385ab6585bff79a50bd5c2b90e2dce74f7 100644 (file)
--- a/lib/sata/test/link_tb.py
+++ b/lib/sata/test/link_tb.py
@@ -5,7 +5,7 @@ from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
 from lib.sata.std import *
-from lib.sata.link import SATALinkLayer
+from lib.sata.link import SATALink
 
 from lib.sata.test.bfm import *
 from lib.sata.test.common import *
@@ -67,7 +67,7 @@ class TB(Module):
        def __init__(self):
                self.submodules.bfm = BFM(phy_debug=False,
                                link_random_level=50, transport_debug=False, transport_loopback=True)
-               self.submodules.link_layer = SATALinkLayer(self.bfm.phy)
+               self.submodules.link = SATALink(self.bfm.phy)
 
                self.submodules.streamer = LinkStreamer()
                streamer_ack_randomizer = AckRandomizer(link_layout(32), level=50)
@@ -77,8 +77,8 @@ class TB(Module):
                self.submodules += logger_ack_randomizer
                self.comb += [
                        Record.connect(self.streamer.source, streamer_ack_randomizer.sink),
-                       Record.connect(streamer_ack_randomizer.source, self.link_layer.sink),
-                       Record.connect(self.link_layer.source, logger_ack_randomizer.sink),
+                       Record.connect(streamer_ack_randomizer.source, self.link.sink),
+                       Record.connect(self.link.source, logger_ack_randomizer.sink),
                        Record.connect(logger_ack_randomizer.source, self.logger.sink)
                ]
 

diff --git a/lib/sata/test/transport_tb.py b/lib/sata/test/transport_tb.py
index ff35d8e31ab0505223486a19fb79c363a36413b9..699f359d08057688fad7f54cd25131ba637f031e 100644 (file)
--- a/lib/sata/test/transport_tb.py
+++ b/lib/sata/test/transport_tb.py
@@ -5,8 +5,8 @@ from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
 from lib.sata.std import *
-from lib.sata.link import SATALinkLayer
-from lib.sata.transport import SATATransportLayer
+from lib.sata.link import SATALink
+from lib.sata.transport import SATATransport
 
 from lib.sata.test.bfm import *
 from lib.sata.test.common import *
@@ -15,8 +15,8 @@ class TB(Module):
        def __init__(self):
                self.submodules.bfm = BFM(phy_debug=False,
                                link_random_level=0, transport_debug=True, transport_loopback=True)
-               self.submodules.link = SATALinkLayer(self.bfm.phy)
-               self.submodules.transport = SATATransportLayer(self.link)
+               self.submodules.link = SATALink(self.bfm.phy)
+               self.submodules.transport = SATATransport(self.link)
 
        def gen_simulation(self, selfp):
                for i in range(100):

diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py
index c89e750fe69060651835a262c7ee27b2e949cf0c..d21ff523ec55f87ee35fc5f6a1b906e5a3ae0be3 100644 (file)
--- a/lib/sata/transport/__init__.py
+++ b/lib/sata/transport/__init__.py
@@ -18,7 +18,7 @@ def _encode_cmd(obj, layout, signal):
                r.append(signal[start:end].eq(item))
        return r
 
-class SATATransportLayerTX(Module):
+class SATATransportTX(Module):
        def __init__(self, link):
                self.sink = sink = Sink(transport_tx_layout(32))
 
@@ -136,7 +136,7 @@ def _decode_cmd(signal, layout, obj):
                r.append(item.eq(signal[start:end]))
        return r
 
-class SATATransportLayerRX(Module):
+class SATATransportRX(Module):
        def __init__(self, link):
                self.source = source = Source(transport_rx_layout(32))
 
@@ -274,8 +274,8 @@ class SATATransportLayerRX(Module):
                self.comb += cmd_done.eq(cnt==cmd_len)
                self.comb += link.source.ack.eq(cmd_receive | (data_receive & source.ack))
 
-class SATATransportLayer(Module):
+class SATATransport(Module):
        def __init__(self, link):
-               self.submodules.tx = SATATransportLayerTX(link)
-               self.submodules.rx = SATATransportLayerRX(link)
+               self.submodules.tx = SATATransportTX(link)
+               self.submodules.rx = SATATransportRX(link)
                self.sink, self.source = self.tx.sink, self.rx.source