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+Date: Fri, 13 Mar 2020 12:56:08 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre Shakti M-Class
+X-Bugzilla-Component: Specification
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-240-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 240] New: POWER-RISCV ISA switch formal
+ standard writeup needed
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