type=LinuxArmSystem
children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
+boot_loader=
+boot_loader_mem=Null
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
+flags_addr=0
+gic_cpu_addr=0
init_param=0
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
+midr_regval=890236928
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[5]
+mem_side=system.membus.port[6]
[system.l2c]
type=BaseCache
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.membus]
type=Bus
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.realview]
type=RealView
-children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
system=system
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
type=IsaFake
pio_addr=1073741824
pio_latency=1000
-pio_size=67108864
+pio_size=536870912
platform=system.realview
ret_bad_addr=false
ret_data16=65535
cpu_pio_delay=10000
dist_addr=520097792
dist_pio_delay=10000
+int_latency=10000
it_lines=128
platform=system.realview
system=system
[system.realview.realview_io]
type=RealViewCtrl
+idreg=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
For more information see: http://www.m5sim.org/warn/23a3c326
warn: The csselr register isn't implemented.
For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
For more information see: http://www.m5sim.org/warn/2c4acb9c
warn: instruction 'mcr dccimvac' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled May 1 2011 21:51:08
-M5 started May 1 2011 21:52:01
+M5 compiled May 2 2011 15:06:32
+M5 started May 2 2011 15:06:36
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 82642207500 because m5_exit instruction encountered
+Exiting @ tick 82662703500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 118050 # Simulator instruction rate (inst/s)
-host_mem_usage 388868 # Number of bytes of host memory used
-host_seconds 439.34 # Real time elapsed on the host
-host_tick_rate 188104852 # Simulator tick rate (ticks/s)
+host_inst_rate 157394 # Simulator instruction rate (inst/s)
+host_mem_usage 389256 # Number of bytes of host memory used
+host_seconds 329.61 # Real time elapsed on the host
+host_tick_rate 250791706 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51864248 # Number of instructions simulated
-sim_seconds 0.082642 # Number of seconds simulated
-sim_ticks 82642207500 # Number of ticks simulated
+sim_insts 51877985 # Number of instructions simulated
+sim_seconds 0.082663 # Number of seconds simulated
+sim_ticks 82662703500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 9217139 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 11723346 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 156768 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 663592 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 11213737 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 13194323 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 788661 # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts 639897 # The number of times a branch was mispredicted
-system.cpu.commit.branches 8427507 # Number of branches committed
-system.cpu.commit.bw_lim_events 797883 # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 9219891 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 11725604 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 157156 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 663969 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 11218057 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 13199466 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 789166 # Number of times the RAS was used to get a target.
+system.cpu.commit.branchMispredicts 640286 # The number of times a branch was mispredicted
+system.cpu.commit.branches 8429112 # Number of branches committed
+system.cpu.commit.bw_lim_events 798153 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts 51987478 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 2962739 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 16084299 # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples 93469913 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.556195 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.349609 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 52001215 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 2962888 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 16092788 # The number of squashed insts skipped by commit
+system.cpu.commit.committed_per_cycle::samples 93510390 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.556101 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.349439 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 71838189 76.86% 76.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 10610207 11.35% 88.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3480363 3.72% 91.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1644006 1.76% 93.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3523448 3.77% 97.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 741299 0.79% 98.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 540450 0.58% 98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 294068 0.31% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 797883 0.85% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 71869411 76.86% 76.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 10616143 11.35% 88.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3483966 3.73% 91.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 1643130 1.76% 93.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 3524025 3.77% 97.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 741321 0.79% 98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 539866 0.58% 98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 294375 0.31% 99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 798153 0.85% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 93469913 # Number of insts commited each cycle
-system.cpu.commit.count 51987478 # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 93510390 # Number of insts commited each cycle
+system.cpu.commit.count 52001215 # Number of instructions committed
system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions.
-system.cpu.commit.function_calls 529811 # Number of function calls committed.
-system.cpu.commit.int_insts 42411675 # Number of committed integer instructions.
-system.cpu.commit.loads 9176268 # Number of loads committed
+system.cpu.commit.function_calls 530196 # Number of function calls committed.
+system.cpu.commit.int_insts 42424846 # Number of committed integer instructions.
+system.cpu.commit.loads 9179779 # Number of loads committed
system.cpu.commit.membars 3 # Number of memory barriers committed
-system.cpu.commit.refs 16251703 # Number of memory references committed
+system.cpu.commit.refs 16257314 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.committedInsts 51864248 # Number of Instructions Simulated
-system.cpu.committedInsts_total 51864248 # Number of Instructions Simulated
-system.cpu.cpi 3.186866 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.186866 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0 111590 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 111590 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14996.059342 # average LoadLockedReq miss latency
+system.cpu.committedInsts 51877985 # Number of Instructions Simulated
+system.cpu.committedInsts_total 51877985 # Number of Instructions Simulated
+system.cpu.cpi 3.186812 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.186812 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0 111585 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 111585 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.470534 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11857.982282 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 105119 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 105119 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 97039500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.057989 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 6471 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 6471 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 940 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65586500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049565 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11849.665522 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0 105103 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 105103 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 97071000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058090 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 6482 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 6482 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits 951 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65540500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049568 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 5531 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 9392794 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9392794 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14764.348504 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0 9397671 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9397671 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14774.624992 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13258.945954 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13259.657075 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 8903858 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 8903858 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 7218821500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.052054 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 488936 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 488936 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 240332 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3296227000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026468 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 8908615 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 8908615 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 7225619000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.052040 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 489056 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 489056 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 240430 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3296695500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026456 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 248604 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38194550500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 105035 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 105035 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 105035 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 105035 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6661106 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6661106 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 39940.947710 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_mshr_misses 248626 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199517000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0 105030 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 105030 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0 105030 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 105030 # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0 6663090 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6663090 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 39945.828494 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38496.257162 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38492.934326 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 4616668 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4616668 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 81656791255 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.306922 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 2044438 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2044438 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1873841 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 6567345983 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025611 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0 4618865 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4618865 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 81658261253 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.306798 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 2044225 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2044225 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1873609 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 6567510483 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025606 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 170597 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 940602193 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7422.728541 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 22666.666667 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 32.464127 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 932 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 30 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 6917983 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 680000 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 170616 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 943852693 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 7367.210748 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 25538.461538 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 32.477815 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 949 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 6991483 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 664000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 16053900 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 16060761 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 16053900 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 35081.915562 # average overall miss latency
+system.cpu.dcache.demand_accesses::total 16060761 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 35086.467018 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23529.459574 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 13520526 # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23528.668366 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0 13527480 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13520526 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 88875612755 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.157804 # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total 13527480 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 88883880253 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0 0.157731 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 2533374 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 2533281 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2533374 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2114173 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9863572983 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.026112 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total 2533281 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2114039 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 9864205983 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.026103 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 419201 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 419242 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 511.750704 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 511.750766 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999513 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0 16053900 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::0 16060761 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 16053900 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 35081.915562 # average overall miss latency
+system.cpu.dcache.overall_accesses::total 16060761 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 35086.467018 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23529.459574 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23528.668366 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 13520526 # number of overall hits
+system.cpu.dcache.overall_hits::0 13527480 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13520526 # number of overall hits
-system.cpu.dcache.overall_miss_latency 88875612755 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.157804 # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total 13527480 # number of overall hits
+system.cpu.dcache.overall_miss_latency 88883880253 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0 0.157731 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 2533374 # number of overall misses
+system.cpu.dcache.overall_misses::0 2533281 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 2533374 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2114173 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9863572983 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.026112 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_misses::total 2533281 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2114039 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 9864205983 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0 0.026103 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 419201 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 39135152693 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses 419242 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 39143369693 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 422493 # number of replacements
-system.cpu.dcache.sampled_refs 423005 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 422530 # number of replacements
+system.cpu.dcache.sampled_refs 423042 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.750704 # Cycle average of tags in use
-system.cpu.dcache.total_refs 13732488 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 511.750766 # Cycle average of tags in use
+system.cpu.dcache.total_refs 13739480 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 390869 # number of writebacks
-system.cpu.decode.BlockedCycles 53918623 # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred 70743 # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved 1221974 # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts 76222777 # Number of instructions handled by decode
-system.cpu.decode.IdleCycles 23898664 # Number of cycles decode is idle
-system.cpu.decode.RunCycles 14467362 # Number of cycles decode is running
-system.cpu.decode.SquashCycles 2560103 # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts 235239 # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles 1185236 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 35200912 # DTB accesses
-system.cpu.dtb.align_faults 1566 # Number of TLB faults due to alignment restrictions
+system.cpu.dcache.writebacks 390905 # number of writebacks
+system.cpu.decode.BlockedCycles 53935385 # Number of cycles decode is blocked
+system.cpu.decode.BranchMispred 70801 # Number of times decode detected a branch misprediction
+system.cpu.decode.BranchResolved 1222673 # Number of times decode resolved a branch
+system.cpu.decode.DecodedInsts 76253610 # Number of instructions handled by decode
+system.cpu.decode.IdleCycles 23916717 # Number of cycles decode is idle
+system.cpu.decode.RunCycles 14472094 # Number of cycles decode is running
+system.cpu.decode.SquashCycles 2561252 # Number of cycles decode is squashing
+system.cpu.decode.SquashedInsts 234958 # Number of squashed instructions handled by decode
+system.cpu.decode.UnblockCycles 1186166 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 35208809 # DTB accesses
+system.cpu.dtb.align_faults 1597 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2768 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 2756 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 35128520 # DTB hits
+system.cpu.dtb.hits 35136197 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 72392 # DTB misses
-system.cpu.dtb.perms_faults 1141 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 1038 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 27711875 # DTB read accesses
-system.cpu.dtb.read_hits 27650210 # DTB read hits
-system.cpu.dtb.read_misses 61665 # DTB read misses
-system.cpu.dtb.write_accesses 7489037 # DTB write accesses
-system.cpu.dtb.write_hits 7478310 # DTB write hits
-system.cpu.dtb.write_misses 10727 # DTB write misses
-system.cpu.fetch.Branches 13194323 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 6536368 # Number of cache lines fetched
-system.cpu.fetch.Cycles 16040697 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 256520 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 63901338 # Number of instructions fetch has processed
-system.cpu.fetch.ItlbSquashes 4100 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.MiscStallCycles 17647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 1039734 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 7258 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.branchRate 0.079828 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 6534883 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 10005800 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.386614 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 96029988 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.819324 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.073932 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.misses 72612 # DTB misses
+system.cpu.dtb.perms_faults 1160 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 1027 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 27716932 # DTB read accesses
+system.cpu.dtb.read_hits 27655119 # DTB read hits
+system.cpu.dtb.read_misses 61813 # DTB read misses
+system.cpu.dtb.write_accesses 7491877 # DTB write accesses
+system.cpu.dtb.write_hits 7481078 # DTB write hits
+system.cpu.dtb.write_misses 10799 # DTB write misses
+system.cpu.fetch.Branches 13199466 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 6541408 # Number of cache lines fetched
+system.cpu.fetch.Cycles 16046672 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 257127 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 63922910 # Number of instructions fetch has processed
+system.cpu.fetch.ItlbSquashes 4120 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.MiscStallCycles 17774 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 1040401 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 7293 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.branchRate 0.079839 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 6539916 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 10009057 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.386649 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 96071614 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.819308 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.074078 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 80005841 83.31% 83.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1273067 1.33% 84.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1748855 1.82% 86.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1275883 1.33% 87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4729341 4.92% 92.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 797324 0.83% 93.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 838519 0.87% 94.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 743131 0.77% 95.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4618027 4.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 80041495 83.31% 83.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1277020 1.33% 84.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1747355 1.82% 86.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1275318 1.33% 87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4729503 4.92% 92.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 796752 0.83% 93.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 838393 0.87% 94.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 743786 0.77% 95.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4621992 4.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 96029988 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 5517 # number of floating regfile reads
-system.cpu.fp_regfile_writes 1898 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses::0 6536276 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 6536276 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14765.188780 # average ReadReq miss latency
+system.cpu.fetch.rateDist::total 96071614 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 5589 # number of floating regfile reads
+system.cpu.fp_regfile_writes 1920 # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses::0 6541316 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 6541316 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14764.035941 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12018.413931 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12016.810358 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_hits::0 5990561 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5990561 # number of ReadReq hits
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-system.cpu.icache.ReadReq_miss_rate::0 0.083490 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 545715 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 545715 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 43351 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 6037618496 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076858 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_hits::0 5995343 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5995343 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 8060764995 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0 0.083465 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0 545973 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 545973 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 43426 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 6039011995 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076827 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 502364 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 502547 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable_latency 4957500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.avg_blocked_cycles::no_mshrs 7107.483871 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 7482.701149 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 11.925573 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 93 # number of cycles access was blocked
+system.cpu.icache.avg_refs 11.930746 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 660996 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 650995 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 6536276 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0 6541316 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 6536276 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14765.188780 # average overall miss latency
+system.cpu.icache.demand_accesses::total 6541316 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14764.035941 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12018.413931 # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 5990561 # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 12016.810358 # average overall mshr miss latency
+system.cpu.icache.demand_hits::0 5995343 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5990561 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 8057584995 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.083490 # miss rate for demand accesses
+system.cpu.icache.demand_hits::total 5995343 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 8060764995 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0 0.083465 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 545715 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0 545973 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 545715 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 43351 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 6037618496 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.076858 # mshr miss rate for demand accesses
+system.cpu.icache.demand_misses::total 545973 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 43426 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 6039011995 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0 0.076827 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 502364 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 502547 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 496.613032 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.969947 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0 6536276 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0 496.616847 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.969955 # Average percentage of cache occupancy
+system.cpu.icache.overall_accesses::0 6541316 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 6536276 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14765.188780 # average overall miss latency
+system.cpu.icache.overall_accesses::total 6541316 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14764.035941 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12018.413931 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12016.810358 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 5990561 # number of overall hits
+system.cpu.icache.overall_hits::0 5995343 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 5990561 # number of overall hits
-system.cpu.icache.overall_miss_latency 8057584995 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.083490 # miss rate for overall accesses
+system.cpu.icache.overall_hits::total 5995343 # number of overall hits
+system.cpu.icache.overall_miss_latency 8060764995 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0 0.083465 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 545715 # number of overall misses
+system.cpu.icache.overall_misses::0 545973 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 545715 # number of overall misses
-system.cpu.icache.overall_mshr_hits 43351 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 6037618496 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.076858 # mshr miss rate for overall accesses
+system.cpu.icache.overall_misses::total 545973 # number of overall misses
+system.cpu.icache.overall_mshr_hits 43426 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 6039011995 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0 0.076827 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 502364 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 502547 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 4957500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 501817 # number of replacements
-system.cpu.icache.sampled_refs 502329 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 502000 # number of replacements
+system.cpu.icache.sampled_refs 502512 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 496.613032 # Cycle average of tags in use
-system.cpu.icache.total_refs 5990561 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 496.616847 # Cycle average of tags in use
+system.cpu.icache.total_refs 5995343 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 6206760000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 41345 # number of writebacks
-system.cpu.idleCycles 69254428 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts 709509 # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches 10208989 # Number of branches executed
-system.cpu.iew.exec_nop 166594 # number of nop insts executed
-system.cpu.iew.exec_rate 0.475153 # Inst execution rate
-system.cpu.iew.exec_refs 35930461 # number of memory reference insts executed
-system.cpu.iew.exec_stores 7787986 # Number of stores executed
+system.cpu.icache.writebacks 41552 # number of writebacks
+system.cpu.idleCycles 69253794 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.branchMispredicts 710007 # Number of branch mispredicts detected at execute
+system.cpu.iew.exec_branches 10210898 # Number of branches executed
+system.cpu.iew.exec_nop 166890 # number of nop insts executed
+system.cpu.iew.exec_rate 0.475154 # Inst execution rate
+system.cpu.iew.exec_refs 35938773 # number of memory reference insts executed
+system.cpu.iew.exec_stores 7790783 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.iewBlockCycles 21409997 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 12801352 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 4001963 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 354229 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 8717928 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 70324411 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 28142475 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1056013 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 78535348 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 28684 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewBlockCycles 21412394 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 12805909 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 4002276 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 355591 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 8720984 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 70347510 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 28147990 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1057037 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 78555101 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 28690 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 45618 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 2560103 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 263512 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 45651 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 2561252 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 263680 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked 8416 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads 328766 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses 7567 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.cacheBlocked 8400 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads 328416 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses 7668 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation 279979 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads 17000828 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads 3625084 # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores 1642493 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 279979 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 185766 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 523743 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers 62153325 # num instructions consuming a value
-system.cpu.iew.wb_count 60744260 # cumulative count of insts written-back
-system.cpu.iew.wb_fanout 0.509987 # average fanout of values written-back
+system.cpu.iew.lsq.thread0.memOrderViolation 280189 # Number of memory ordering violations
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+system.cpu.iew.lsq.thread0.squashedLoads 3626130 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores 1643449 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 280189 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 185530 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 524477 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.wb_consumers 62170053 # num instructions consuming a value
+system.cpu.iew.wb_count 60762788 # cumulative count of insts written-back
+system.cpu.iew.wb_fanout 0.510007 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers 31697370 # num instructions producing a value
-system.cpu.iew.wb_rate 0.367514 # insts written-back per cycle
-system.cpu.iew.wb_sent 78012051 # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads 182457772 # number of integer regfile reads
-system.cpu.int_regfile_writes 43778590 # number of integer regfile writes
-system.cpu.ipc 0.313788 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.313788 # IPC: Total IPC of All Threads
+system.cpu.iew.wb_producers 31707186 # num instructions producing a value
+system.cpu.iew.wb_rate 0.367534 # insts written-back per cycle
+system.cpu.iew.wb_sent 78030912 # cumulative count of insts sent to commit
+system.cpu.int_regfile_reads 182505983 # number of integer regfile reads
+system.cpu.int_regfile_writes 43793404 # number of integer regfile writes
+system.cpu.ipc 0.313793 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.313793 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 2393223 3.01% 3.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 40680159 51.11% 54.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 71135 0.09% 54.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 40692276 51.11% 54.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 71186 0.09% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 15 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 54.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 880 0.00% 54.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 881 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.21% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 54.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.21% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 28494301 35.80% 90.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7951639 9.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 28499876 35.80% 90.01% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 79591361 # Type of FU issued
-system.cpu.iq.fp_alu_accesses 8649 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 16528 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 6413 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 9518 # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt 4821398 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.060577 # FU busy rate (busy events/executed inst)
+system.cpu.iq.FU_type_0::total 79612138 # Type of FU issued
+system.cpu.iq.fp_alu_accesses 8660 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 16534 # Number of floating instruction queue reads
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+system.cpu.iq.fp_inst_queue_writes 9494 # Number of floating instruction queue writes
+system.cpu.iq.fu_busy_cnt 4821134 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.060558 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5422 0.11% 0.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5360 0.11% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 4503057 93.40% 93.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 312919 6.49% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 4502804 93.40% 93.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 312970 6.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses 82010887 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 260214449 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 60737847 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 88009636 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 66125775 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 79591361 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 4032042 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 17595997 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 124696 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 1069303 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 22170829 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples 96029988 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.828818 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.378506 # Number of insts issued each cycle
+system.cpu.iq.int_alu_accesses 82031389 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 260297363 # Number of integer instruction queue reads
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+system.cpu.iq.int_inst_queue_writes 88040036 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 66148270 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 79612138 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 4032350 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 17603379 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 124488 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 1069462 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 22177627 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.issued_per_cycle::samples 96071614 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.828675 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.378358 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 59877651 62.35% 62.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 16701073 17.39% 79.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7167891 7.46% 87.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4116385 4.29% 91.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5937883 6.18% 97.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1300941 1.35% 99.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 620651 0.65% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 234896 0.24% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 72617 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 59906627 62.36% 62.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 16708495 17.39% 79.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7171843 7.47% 87.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4115905 4.28% 91.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5939256 6.18% 97.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1302334 1.36% 99.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 619107 0.64% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 235470 0.25% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 72577 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 96029988 # Number of insts issued each cycle
-system.cpu.iq.rate 0.481542 # Inst issue rate
-system.cpu.itb.accesses 6549493 # DTB accesses
+system.cpu.iq.issued_per_cycle::total 96071614 # Number of insts issued each cycle
+system.cpu.iq.rate 0.481548 # Inst issue rate
+system.cpu.itb.accesses 6554572 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1627 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 1626 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 6542235 # DTB hits
-system.cpu.itb.inst_accesses 6549493 # ITB inst accesses
-system.cpu.itb.inst_hits 6542235 # ITB inst hits
-system.cpu.itb.inst_misses 7258 # ITB inst misses
-system.cpu.itb.misses 7258 # DTB misses
-system.cpu.itb.perms_faults 5302 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.hits 6547279 # DTB hits
+system.cpu.itb.inst_accesses 6554572 # ITB inst accesses
+system.cpu.itb.inst_hits 6547279 # ITB inst hits
+system.cpu.itb.inst_misses 7293 # ITB inst misses
+system.cpu.itb.misses 7293 # DTB misses
+system.cpu.itb.perms_faults 5323 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.memDep0.conflictingLoads 527 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1505 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 12801352 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8717928 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 84103631 # number of misc regfile reads
-system.cpu.misc_regfile_writes 505277 # number of misc regfile writes
-system.cpu.numCycles 165284416 # number of cpu cycles simulated
+system.cpu.memDep0.insertedLoads 12805909 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8720984 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 84139545 # number of misc regfile reads
+system.cpu.misc_regfile_writes 512625 # number of misc regfile writes
+system.cpu.numCycles 165325408 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.BlockCycles 33115437 # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps 36635967 # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents 774543 # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles 25534118 # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents 2455786 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.BlockCycles 33120031 # Number of cycles rename is blocking
+system.cpu.rename.CommittedMaps 36654067 # Number of HB maps that are committed
+system.cpu.rename.IQFullEvents 775523 # Number of times rename has blocked due to IQ full
+system.cpu.rename.IdleCycles 25553608 # Number of cycles rename is idle
+system.cpu.rename.LSQFullEvents 2458566 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 439444 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups 190012528 # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts 73459196 # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands 53155574 # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles 13048942 # Number of cycles rename is running
-system.cpu.rename.SquashCycles 2560103 # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles 5434449 # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps 16519606 # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups 49943 # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups 189962585 # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles 16336939 # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts 811757 # count of serializing insts renamed
-system.cpu.rename.skidInsts 14251840 # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts 662762 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 159803078 # The number of ROB reads
-system.cpu.rob.rob_writes 138748293 # The number of ROB writes
-system.cpu.timesIdled 1093520 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RenameLookups 190069366 # Number of register rename lookups that rename has made
+system.cpu.rename.RenamedInsts 73481256 # Number of instructions processed by rename
+system.cpu.rename.RenamedOperands 53179946 # Number of destination operands rename has renamed
+system.cpu.rename.RunCycles 13052599 # Number of cycles rename is running
+system.cpu.rename.SquashCycles 2561252 # Number of cycles rename is squashing
+system.cpu.rename.UnblockCycles 5439754 # Number of cycles rename is unblocking
+system.cpu.rename.UndoneMaps 16525878 # Number of HB maps that are undone due to squashing
+system.cpu.rename.fp_rename_lookups 50199 # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups 190019167 # Number of integer rename lookups
+system.cpu.rename.serializeStallCycles 16344370 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializingInsts 812158 # count of serializing insts renamed
+system.cpu.rename.skidInsts 14266692 # count of insts added to the skid buffer
+system.cpu.rename.tempSerializingInsts 663049 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 159865147 # The number of ROB reads
+system.cpu.rob.rob_writes 138793846 # The number of ROB writes
+system.cpu.timesIdled 1093874 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 168895 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 168895 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52452.689806 # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0 168913 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 168913 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52452.525224 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40011.850713 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 60969 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 60969 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 5661009000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.639012 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 107926 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 107926 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4318319000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.639012 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40011.488822 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0 60982 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 60982 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 5661253500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0 0.638974 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 107931 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 107931 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 4318480000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0 0.638974 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 107926 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 754009 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 102736 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 856745 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52493.894964 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 11763824.175824 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 11816318.070788 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40042.808219 # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses 107931 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0 754170 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 103109 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 857279 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 52487.372499 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 12162755.681818 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 12215243.054317 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40042.547465 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 733616 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 102645 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 836261 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 1070508000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.027046 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.000886 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.027932 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 20393 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 91 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 20484 # number of ReadReq misses
+system.l2c.ReadReq_hits::0 733778 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 103021 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 836799 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 1070322500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.027039 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.000853 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.027892 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 20392 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 88 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses
system.l2c.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 818475000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.027108 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.198957 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.226065 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 20440 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 28942346500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 1727 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1727 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 400.236827 # average UpgradeReq miss latency
+system.l2c.ReadReq_mshr_miss_latency 818309500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.027097 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.198198 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.225295 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 20436 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 28946013500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses::0 1731 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1731 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 430.514488 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.977997 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1689 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1689 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 67560000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.977997 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.591366 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0 40 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0 0.976892 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 1691 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1691 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 67641000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.976892 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 1689 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 1691 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 746141450 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 432214 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 432214 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 432214 # number of Writeback hits
-system.l2c.Writeback_hits::total 432214 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 748185950 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0 432457 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 432457 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 432457 # number of Writeback hits
+system.l2c.Writeback_hits::total 432457 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 8.138796 # Average number of references to valid blocks.
+system.l2c.avg_refs 8.161920 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 922904 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 102736 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1025640 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52459.238305 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 73972714.285714 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74025173.524019 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40016.780144 # average overall mshr miss latency
-system.l2c.demand_hits::0 794585 # number of demand (read+write) hits
-system.l2c.demand_hits::1 102645 # number of demand (read+write) hits
-system.l2c.demand_hits::total 897230 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 6731517000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.139038 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.000886 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.139924 # miss rate for demand accesses
-system.l2c.demand_misses::0 128319 # number of demand (read+write) misses
-system.l2c.demand_misses::1 91 # number of demand (read+write) misses
-system.l2c.demand_misses::total 128410 # number of demand (read+write) misses
+system.l2c.demand_accesses::0 923083 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 103109 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1026192 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 52458.062857 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 76495181.818182 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 76547639.881039 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40016.433351 # average overall mshr miss latency
+system.l2c.demand_hits::0 794760 # number of demand (read+write) hits
+system.l2c.demand_hits::1 103021 # number of demand (read+write) hits
+system.l2c.demand_hits::total 897781 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 6731576000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.139016 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.000853 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.139869 # miss rate for demand accesses
+system.l2c.demand_misses::0 128323 # number of demand (read+write) misses
+system.l2c.demand_misses::1 88 # number of demand (read+write) misses
+system.l2c.demand_misses::total 128411 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 44 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 5136794000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.139089 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.249474 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 1.388564 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 128366 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency 5136789500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.139063 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.244964 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 1.384027 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 128367 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 6525.669057 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31523.989164 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.099574 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.481018 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 922904 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 102736 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1025640 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52459.238305 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 73972714.285714 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74025173.524019 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40016.780144 # average overall mshr miss latency
+system.l2c.occ_blocks::0 6522.284105 # Average occupied blocks per context
+system.l2c.occ_blocks::1 31526.690965 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.099522 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.481059 # Average percentage of cache occupancy
+system.l2c.overall_accesses::0 923083 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 103109 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1026192 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52458.062857 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 76495181.818182 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 76547639.881039 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40016.433351 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 794585 # number of overall hits
-system.l2c.overall_hits::1 102645 # number of overall hits
-system.l2c.overall_hits::total 897230 # number of overall hits
-system.l2c.overall_miss_latency 6731517000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.139038 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.000886 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.139924 # miss rate for overall accesses
-system.l2c.overall_misses::0 128319 # number of overall misses
-system.l2c.overall_misses::1 91 # number of overall misses
-system.l2c.overall_misses::total 128410 # number of overall misses
+system.l2c.overall_hits::0 794760 # number of overall hits
+system.l2c.overall_hits::1 103021 # number of overall hits
+system.l2c.overall_hits::total 897781 # number of overall hits
+system.l2c.overall_miss_latency 6731576000 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.139016 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.000853 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.139869 # miss rate for overall accesses
+system.l2c.overall_misses::0 128323 # number of overall misses
+system.l2c.overall_misses::1 88 # number of overall misses
+system.l2c.overall_misses::total 128411 # number of overall misses
system.l2c.overall_mshr_hits 44 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 5136794000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.139089 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.249474 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 1.388564 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 128366 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 29688487950 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency 5136789500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.139063 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.244964 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 1.384027 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 128367 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 29694199450 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 94658 # number of replacements
-system.l2c.sampled_refs 126891 # Sample count of references to valid blocks.
+system.l2c.replacements 94647 # number of replacements
+system.l2c.sampled_refs 126884 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 38049.658221 # Cycle average of tags in use
-system.l2c.total_refs 1032740 # Total number of references to valid blocks.
+system.l2c.tagsinuse 38048.975070 # Cycle average of tags in use
+system.l2c.total_refs 1035617 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 87784 # number of writebacks
+system.l2c.writebacks 87762 # number of writebacks
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-host_inst_rate 137427 # Simulator instruction rate (inst/s)
-host_mem_usage 350244 # Number of bytes of host memory used
-host_seconds 663.99 # Real time elapsed on the host
-host_tick_rate 67463360 # Simulator tick rate (ticks/s)
+host_inst_rate 115565 # Simulator instruction rate (inst/s)
+host_mem_usage 395544 # Number of bytes of host memory used
+host_seconds 789.60 # Real time elapsed on the host
+host_tick_rate 56730912 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91249905 # Number of instructions simulated
sim_seconds 0.044795 # Number of seconds simulated
system.cpu.rename.IdleCycles 35560664 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 1952065 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups 350271207 # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups 350271208 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 135568411 # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands 105865304 # Number of destination operands rename has renamed
+system.cpu.rename.RenamedOperands 105865305 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 30904016 # Number of cycles rename is running
system.cpu.rename.SquashCycles 5457924 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 5891977 # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps 34288334 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 34288335 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 787 # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups 350270420 # Number of integer rename lookups
+system.cpu.rename.int_rename_lookups 350270421 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 9187209 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 701223 # count of serializing insts renamed
system.cpu.rename.skidInsts 13035103 # count of insts added to the skid buffer
---------- Begin Simulation Statistics ----------
-host_inst_rate 116803 # Simulator instruction rate (inst/s)
-host_mem_usage 223612 # Number of bytes of host memory used
-host_seconds 4908.63 # Real time elapsed on the host
-host_tick_rate 67784916 # Simulator tick rate (ticks/s)
+host_inst_rate 95018 # Simulator instruction rate (inst/s)
+host_mem_usage 268868 # Number of bytes of host memory used
+host_seconds 6034.01 # Real time elapsed on the host
+host_tick_rate 55142639 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 573342397 # Number of instructions simulated
sim_seconds 0.332731 # Number of seconds simulated
system.cpu.rename.IdleCycles 293899856 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 10512591 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups 2673538298 # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups 2673538381 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 1068521543 # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands 798521782 # Number of destination operands rename has renamed
+system.cpu.rename.RenamedOperands 798521865 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 223635059 # Number of cycles rename is running
system.cpu.rename.SquashCycles 57332647 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 24492193 # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps 350028044 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 350028127 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 1141 # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups 2673537157 # Number of integer rename lookups
+system.cpu.rename.int_rename_lookups 2673537240 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 49776793 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 2837350 # count of serializing insts renamed
system.cpu.rename.skidInsts 62579735 # count of insts added to the skid buffer
---------- Begin Simulation Statistics ----------
-host_inst_rate 123746 # Simulator instruction rate (inst/s)
-host_mem_usage 223548 # Number of bytes of host memory used
-host_seconds 15235.59 # Real time elapsed on the host
-host_tick_rate 57045555 # Simulator tick rate (ticks/s)
+host_inst_rate 95673 # Simulator instruction rate (inst/s)
+host_mem_usage 268824 # Number of bytes of host memory used
+host_seconds 19706.22 # Real time elapsed on the host
+host_tick_rate 44103983 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1885343131 # Number of instructions simulated
sim_seconds 0.869123 # Number of seconds simulated
system.cpu.rename.IdleCycles 804669593 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 12419294 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups 8858159876 # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups 8858159877 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 3258876297 # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands 2595747724 # Number of destination operands rename has renamed
+system.cpu.rename.RenamedOperands 2595747725 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 616670755 # Number of cycles rename is running
system.cpu.rename.SquashCycles 162682073 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 32941123 # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps 1072021248 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 1072021249 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 417025150 # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups 8441134726 # Number of integer rename lookups
+system.cpu.rename.int_rename_lookups 8441134727 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 88543058 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 8500262 # count of serializing insts renamed
system.cpu.rename.skidInsts 93807403 # count of insts added to the skid buffer
---------- Begin Simulation Statistics ----------
-host_inst_rate 102961 # Simulator instruction rate (inst/s)
-host_mem_usage 269452 # Number of bytes of host memory used
-host_seconds 977.39 # Real time elapsed on the host
-host_tick_rate 40914717 # Simulator tick rate (ticks/s)
+host_inst_rate 123690 # Simulator instruction rate (inst/s)
+host_mem_usage 271412 # Number of bytes of host memory used
+host_seconds 813.59 # Real time elapsed on the host
+host_tick_rate 49152177 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 100633290 # Number of instructions simulated
sim_seconds 0.039990 # Number of seconds simulated
system.cpu.rename.IdleCycles 27131253 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 3054544 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups 315617756 # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups 315617758 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 118187842 # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands 90561212 # Number of destination operands rename has renamed
+system.cpu.rename.RenamedOperands 90561214 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 20595374 # Number of cycles rename is running
system.cpu.rename.SquashCycles 2130818 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 4332267 # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps 14682574 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 14682576 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 83434 # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups 315534322 # Number of integer rename lookups
+system.cpu.rename.int_rename_lookups 315534324 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 21817665 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 758712 # count of serializing insts renamed
system.cpu.rename.skidInsts 12129084 # count of insts added to the skid buffer
type=LinuxArmSystem
children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
+boot_loader=
+boot_loader_mem=Null
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
+flags_addr=0
+gic_cpu_addr=0
init_param=0
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
+midr_regval=890236928
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[5]
+mem_side=system.membus.port[6]
[system.l2c]
type=BaseCache
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.membus]
type=Bus
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.realview]
type=RealView
-children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
system=system
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
type=IsaFake
pio_addr=1073741824
pio_latency=1000
-pio_size=67108864
+pio_size=536870912
platform=system.realview
ret_bad_addr=false
ret_data16=65535
cpu_pio_delay=10000
dist_addr=520097792
dist_pio_delay=10000
+int_latency=10000
it_lines=128
platform=system.realview
system=system
[system.realview.realview_io]
type=RealViewCtrl
+idreg=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
For more information see: http://www.m5sim.org/warn/23a3c326
warn: The csselr register isn't implemented.
For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
For more information see: http://www.m5sim.org/warn/2c4acb9c
warn: instruction 'mcr dccimvac' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled May 1 2011 21:51:08
-M5 started May 1 2011 21:51:14
+M5 compiled May 2 2011 15:06:32
+M5 started May 2 2011 15:06:36
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 26341084000 because m5_exit instruction encountered
+Exiting @ tick 26344863500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1460315 # Simulator instruction rate (inst/s)
-host_mem_usage 380976 # Number of bytes of host memory used
-host_seconds 35.59 # Real time elapsed on the host
-host_tick_rate 740141754 # Simulator tick rate (ticks/s)
+host_inst_rate 2974441 # Simulator instruction rate (inst/s)
+host_mem_usage 381360 # Number of bytes of host memory used
+host_seconds 17.48 # Real time elapsed on the host
+host_tick_rate 1507548482 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51971087 # Number of instructions simulated
-sim_seconds 0.026341 # Number of seconds simulated
-sim_ticks 26341084000 # Number of ticks simulated
+sim_insts 51978646 # Number of instructions simulated
+sim_seconds 0.026345 # Number of seconds simulated
+sim_ticks 26344863500 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7807332 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7807332 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7570991 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7570991 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030272 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 236341 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 236341 # number of ReadReq misses
+system.cpu.dcache.ReadReq_accesses::0 7808976 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 7808976 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0 7572677 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7572677 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.030260 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 236299 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 236299 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6662917 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6662917 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6490820 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6490820 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.025829 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172097 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172097 # number of WriteReq misses
+system.cpu.dcache.WriteReq_accesses::0 6664019 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6664019 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0 6491936 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6491936 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0 0.025823 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 172083 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 172083 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.634545 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 34.645976 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14470249 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 14472995 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14470249 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 14472995 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14061811 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0 14064613 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14061811 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 14064613 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028226 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0 0.028217 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 408438 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 408382 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 408438 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 408382 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 710885 # number of demand (read+write) hits
-system.l2c.demand_hits::1 7047 # number of demand (read+write) hits
-system.l2c.demand_hits::total 717932 # number of demand (read+write) hits
+system.l2c.demand_hits::0 710856 # number of demand (read+write) hits
+system.l2c.demand_hits::1 7045 # number of demand (read+write) hits
+system.l2c.demand_hits::total 717901 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.155500 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.004380 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.159880 # miss rate for demand accesses
-system.l2c.demand_misses::0 130897 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.155507 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.004381 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.159888 # miss rate for demand accesses
+system.l2c.demand_misses::0 130899 # number of demand (read+write) misses
system.l2c.demand_misses::1 31 # number of demand (read+write) misses
-system.l2c.demand_misses::total 130928 # number of demand (read+write) misses
+system.l2c.demand_misses::total 130930 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5062.788087 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31189.705520 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.077252 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.475917 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 841782 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 7078 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 848860 # number of overall (read+write) accesses
+system.l2c.occ_blocks::0 5062.983429 # Average occupied blocks per context
+system.l2c.occ_blocks::1 31189.392245 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.077255 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.475912 # Average percentage of cache occupancy
+system.l2c.overall_accesses::0 841755 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 7076 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 848831 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 710885 # number of overall hits
-system.l2c.overall_hits::1 7047 # number of overall hits
-system.l2c.overall_hits::total 717932 # number of overall hits
+system.l2c.overall_hits::0 710856 # number of overall hits
+system.l2c.overall_hits::1 7045 # number of overall hits
+system.l2c.overall_hits::total 717901 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.155500 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.004380 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.159880 # miss rate for overall accesses
-system.l2c.overall_misses::0 130897 # number of overall misses
+system.l2c.overall_miss_rate::0 0.155507 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.004381 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.159888 # miss rate for overall accesses
+system.l2c.overall_misses::0 130899 # number of overall misses
system.l2c.overall_misses::1 31 # number of overall misses
-system.l2c.overall_misses::total 130928 # number of overall misses
+system.l2c.overall_misses::total 130930 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 97110 # number of replacements
-system.l2c.sampled_refs 129684 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 129685 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36252.493607 # Cycle average of tags in use
-system.l2c.total_refs 871933 # Total number of references to valid blocks.
+system.l2c.tagsinuse 36252.375674 # Cycle average of tags in use
+system.l2c.total_refs 872636 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 91106 # number of writebacks
+system.l2c.writebacks 91105 # number of writebacks
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
+boot_loader=
+boot_loader_mem=Null
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
+flags_addr=0
+gic_cpu_addr=0
init_param=0
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
+midr_regval=890236928
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[5]
+mem_side=system.membus.port[6]
[system.l2c]
type=BaseCache
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.membus]
type=Bus
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
[system.realview]
type=RealView
-children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
system=system
+[system.realview.a9scu]
+type=A9SCU
+pio_addr=520093696
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[5]
+
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
type=IsaFake
pio_addr=1073741824
pio_latency=1000
-pio_size=67108864
+pio_size=536870912
platform=system.realview
ret_bad_addr=false
ret_data16=65535
cpu_pio_delay=10000
dist_addr=520097792
dist_pio_delay=10000
+int_latency=10000
it_lines=128
platform=system.realview
system=system
[system.realview.realview_io]
type=RealViewCtrl
+idreg=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
For more information see: http://www.m5sim.org/warn/23a3c326
warn: The csselr register isn't implemented.
For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
For more information see: http://www.m5sim.org/warn/2c4acb9c
warn: instruction 'mcr dccimvac' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled May 1 2011 21:51:08
-M5 started May 1 2011 21:51:14
+M5 compiled May 2 2011 15:06:32
+M5 started May 2 2011 15:06:36
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 114293937000 because m5_exit instruction encountered
+Exiting @ tick 114316622000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 703032 # Simulator instruction rate (inst/s)
-host_mem_usage 381000 # Number of bytes of host memory used
-host_seconds 72.76 # Real time elapsed on the host
-host_tick_rate 1570917363 # Simulator tick rate (ticks/s)
+host_inst_rate 1535776 # Simulator instruction rate (inst/s)
+host_mem_usage 381388 # Number of bytes of host memory used
+host_seconds 33.31 # Real time elapsed on the host
+host_tick_rate 3431474709 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51149744 # Number of instructions simulated
-sim_seconds 0.114294 # Number of seconds simulated
-sim_ticks 114293937000 # Number of ticks simulated
+sim_insts 51162775 # Number of instructions simulated
+sim_seconds 0.114317 # Number of seconds simulated
+sim_ticks 114316622000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 7812826 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7812826 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.475503 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0 7815759 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 7815759 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.214184 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12651.150503 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12650.891296 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7574365 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7574365 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3732266500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.030522 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 238461 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 238461 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3016806000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030522 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 7577286 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7577286 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3732392000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.030512 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 238473 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 238473 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3016896000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030512 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 238461 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38192110000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_misses 238473 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38196735000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6665523 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6665523 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 40729.480776 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0 6667481 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6667481 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.618008 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37729.274596 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.411843 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 6493343 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6493343 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 7012802000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.025831 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172180 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172180 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 6496226500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025831 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0 6495289 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6495289 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 7012970000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.025826 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 172192 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 172192 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 6496358500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025826 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 172180 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927806000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_misses 172192 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 931126000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.459827 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 34.469586 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14478349 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 14483240 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14478349 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26166.574940 # average overall miss latency
+system.cpu.dcache.demand_accesses::total 14483240 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26165.760413 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14067708 # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0 14072575 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14067708 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10745068500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028362 # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total 14072575 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10745362000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0 0.028354 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 410641 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 410665 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 410641 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 410665 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9513032500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.028362 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency 9513254500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.028354 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 410641 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 410665 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 509.188646 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.994509 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0 14478349 # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0 509.189203 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.994510 # Average percentage of cache occupancy
+system.cpu.dcache.overall_accesses::0 14483240 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14478349 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 14067708 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 410641 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 413448 # number of replacements
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 509.188646 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14264990 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 382785 # number of writebacks
-system.cpu.dtb.accesses 15507021 # DTB accesses
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+system.cpu.dtb.accesses 15512082 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15501368 # DTB hits
+system.cpu.dtb.hits 15506431 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5653 # DTB misses
+system.cpu.dtb.misses 5651 # DTB misses
system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8728602 # DTB read accesses
-system.cpu.dtb.read_hits 8723916 # DTB read hits
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-system.cpu.dtb.write_accesses 6778419 # DTB write accesses
-system.cpu.dtb.write_hits 6777452 # DTB write hits
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system.cpu.dtb.write_misses 967 # DTB write misses
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-system.cpu.icache.ReadReq_accesses::total 41474839 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.569871 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 433974 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 5116703000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.010464 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 433974 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 484.306355 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.945911 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0 41474839 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0 484.311851 # Average occupied blocks per context
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 41040865 # number of overall hits
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system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.icache.overall_misses::1 0 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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+system.cpu.icache.overall_mshr_miss_latency 5116910500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 433974 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 433462 # number of replacements
-system.cpu.icache.sampled_refs 433974 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 433477 # number of replacements
+system.cpu.icache.sampled_refs 433989 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 484.306355 # Cycle average of tags in use
-system.cpu.icache.total_refs 41040865 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 484.311851 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 34334 # number of writebacks
+system.cpu.icache.writebacks 34328 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41477769 # DTB accesses
+system.cpu.itb.accesses 41486666 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41474839 # DTB hits
-system.cpu.itb.inst_accesses 41477769 # ITB inst accesses
-system.cpu.itb.inst_hits 41474839 # ITB inst hits
+system.cpu.itb.hits 41483736 # DTB hits
+system.cpu.itb.inst_accesses 41486666 # ITB inst accesses
+system.cpu.itb.inst_hits 41483736 # ITB inst hits
system.cpu.itb.inst_misses 2930 # ITB inst misses
system.cpu.itb.misses 2930 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 228587874 # number of cpu cycles simulated
+system.cpu.numCycles 228633244 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 228587874 # Number of busy cycles
-system.cpu.num_conditional_control_insts 7014796 # number of instructions that are conditional controls
+system.cpu.num_busy_cycles 228633244 # Number of busy cycles
+system.cpu.num_conditional_control_insts 7015568 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
system.cpu.num_fp_insts 6058 # number of float instructions
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
-system.cpu.num_func_calls 1108768 # number of times a function call or return occured
+system.cpu.num_func_calls 1109778 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 51149744 # Number of instructions executed
-system.cpu.num_int_alu_accesses 42422684 # Number of integer alu accesses
-system.cpu.num_int_insts 42422684 # number of integer instructions
-system.cpu.num_int_register_reads 139100376 # number of times the integer registers were read
-system.cpu.num_int_register_writes 34478872 # number of times the integer registers were written
-system.cpu.num_load_insts 9179491 # Number of load instructions
-system.cpu.num_mem_refs 16255504 # number of memory refs
-system.cpu.num_store_insts 7076013 # Number of store instructions
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+system.cpu.num_int_insts 42435662 # number of integer instructions
+system.cpu.num_int_register_reads 139138635 # number of times the integer registers were read
+system.cpu.num_int_register_writes 34495190 # number of times the integer registers were written
+system.cpu.num_load_insts 9182978 # Number of load instructions
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+system.cpu.num_store_insts 7078093 # Number of store instructions
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 170341 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170341 # number of ReadExReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::total 170353 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 62544 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 62544 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::0 62556 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 62556 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.632831 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.632786 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.632831 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.632786 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 675421 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles
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system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses
system.l2c.ReadReq_misses::1 22 # number of ReadReq misses
system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 29200759000 # number of ReadReq MSHR uncacheable cycles
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system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 741108000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 417119 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 417119 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 417119 # number of Writeback hits
-system.l2c.Writeback_hits::total 417119 # number of Writeback hits
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+system.l2c.Writeback_hits::total 417140 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 7.066815 # Average number of references to valid blocks.
+system.l2c.avg_refs 7.067586 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 845762 # number of demand (read+write) accesses
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system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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-system.l2c.demand_hits::1 6166 # number of demand (read+write) hits
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system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.148738 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.003555 # miss rate for demand accesses
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system.l2c.demand_misses::0 125797 # number of demand (read+write) misses
system.l2c.demand_misses::1 22 # number of demand (read+write) misses
system.l2c.demand_misses::total 125819 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.148764 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5338.149518 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31318.985652 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.081454 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.477890 # Average percentage of cache occupancy
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-system.l2c.overall_accesses::total 851950 # number of overall (read+write) accesses
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system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 719965 # number of overall hits
-system.l2c.overall_hits::1 6166 # number of overall hits
-system.l2c.overall_hits::total 726131 # number of overall hits
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system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.148738 # miss rate for overall accesses
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system.l2c.overall_misses::0 125797 # number of overall misses
system.l2c.overall_misses::1 22 # number of overall misses
system.l2c.overall_misses::total 125819 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_rate::1 20.332741 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 20.481505 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::1 20.319606 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 20.468363 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 29941867000 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 93108 # number of replacements
+system.l2c.replacements 93111 # number of replacements
system.l2c.sampled_refs 124568 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36657.135171 # Cycle average of tags in use
-system.l2c.total_refs 880299 # Total number of references to valid blocks.
+system.l2c.tagsinuse 36656.816071 # Cycle average of tags in use
+system.l2c.total_refs 880395 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 87346 # number of writebacks
+system.l2c.writebacks 87350 # number of writebacks
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff